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TLK106L: FCS errors on receiving side for PHY sourced frames

Oleg Tabarovskiy
Prodigy 80 points
Part Number: TLK106L
Other Parts Discussed in Thread: TLK106

Hi !

We are using TLK106L as a PHY together with STM32F407 MCU. After several hours after PHY reset number of FCS errors for frames transmitted by PHY is rising from zero to 10-15% of total number of sent frames. After reset situation repeats, immediately after reset number of FCS errors on receiving side is 0 and then goes to 10-15%. Behaviour is the same with different models of ethernet switches.

PHY initialization sequence:
- write 0x8000 to reg0 (BMCR) - software reset
- small delay
- write 0x0000 to reg0 (BMCR) - set 10HALF mode (not really needed, caused by software structure)
- some delay
- write 0x1000 to reg0 (BMCR) - enable AutoNegotiation
- wait until Link established by polling reg1 (BMSR) bit 2(Link Status)

We are using external 50 MHz oscillator.

BR Oleg

  • 0
    TI__Mastermind 19780 points
    Hi Oleg,

    You mention FCS, and I assume you mean frame check sequence. This means the CRC field in the Ethernet frame indicates an error. Is that correct? Or do you mean there is a false carrier event occurring as reported by the switch? Both of these are a little different. False carrier indicates a problem with the reference clock to the TLK106L. CRC indicates an issue with data transmission.

    Can you provide a schematic of the TLK106L solution?

    Can you provide a datasheet on the 50MHz oscillator?

    I'd also like to see a register dump in the case where errors are 0%, and anothe register dump when errors are 10% - 15%

    Please include all registers in the datasheet. Keep in mind that registers with addresses higher than 0x1F require access by the extended register access method described in the datasheet.

    Best Regards,
  • 0 in reply to Rob Rodrigues
    Prodigy 80 points

    Hi Rob,

    thanks for your answer. Regarding the FCS - your are right, switch detects CRC error, at least this is how it is reported. Strictly speaking models we are using do not have special counter for false carrier event errors.

    I attached schematic and oscillator datasheet. In order to get register dump we need to add instrumentation to code which will take time.

    I forgot to tell that we are also using TLK106  (without L) in later variation of the product (with exactly the same schematic of the ethernet part) and it never experience problems we have with TLK106L. Probably this information could be useful.

    BR Olegethernet.pdfGEYER-KXO-V97-V2.pdf