I'm trying to design a TTL to LVDS interface using SN65LVDS391 IC. I'm making the PCB a 4 layer board, with top layer for lvds, bottom for TTL, layer 2 for ground and layer 3 for power. The data sheet says to keep the separation between ground and power plane as 5 mils. But standard core sizes are around 47 mils. If i do change this to the separation suggested by TI, I have to increase the size of my dielectric spacing between the top and layer 2, and bottom and layer 3. I'm using sma connectors in the design, so i'm not sure if i reduce the board thickness further, will there be enough support mechanically.
Is there a reference/layout stack up that is recommended by TI for these ICs ?
It would be great if someone is able to guide !