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PCA9536: one question about the POR function of PCA9536

Part Number: PCA9536
Other Parts Discussed in Thread: TCA9536

Hi

One customer has question for the POR function of PCA9536. Can you help to check and give some comments? Thanks.

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We noticed an errata in TI PCA9536 datasheet, stating chip lockup if exposed to undesired PoR sequence. Would like to get some elaboration on the exact behavior of such lockup? E.g. unresponsive device? Unexpected reg / pin value? Or something else…

  • Hi Oliver,

    The internal digital logic (including I2C state machine) would not be properly initialized, and so the register values would not be well-defined and attempted I2C transactions would result in a NACK/unresponsive device.

    Max
  • Hi Max,

    In our application the LDO feeding the PCA9536 is powered off the Power supply V12 output, which is typically having a ramp rate in the neighborhood of 20mS to 40ms. As a result the PCA9536 sees a power slope of 20ms to 40ms.

    The chip is intermittently behaving abnormally. The symptom is that the pins are occasionally set to output driving low, while they shall stay input by default. However to note, the chip has been never unresponsive, and a subsequent write to the affected registers is able to fix the setting. Is this expected?

    Thanks,
    Sandburg

  • Hey Sandburg,

    " The symptom is that the pins are occasionally set to output driving low, while they shall stay input by default. However to note, the chip has been never unresponsive, and a subsequent write to the affected registers is able to fix the setting. Is this expected?"


    I believe this is due to the POR requirements not being met. What I have seen when the POR requirements are violated for this device is the device will improperly start up with the wrong internal register settings such as: random bits in the configuration starting as an output.

    "In our application the LDO feeding the PCA9536 is powered off the Power supply V12 output, which is typically having a ramp rate in the neighborhood of 20mS to 40ms. As a result the PCA9536 sees a power slope of 20ms to 40ms."


    This sounds like you are violating the POR requirements as the rise time from off to Vcc needs to be under 10ms. If you have any decoupling caps on Vcc to our device then I would suggest removing them to help with the rise time.

    Alternatively we do have other IO expanders with the TCA name which have much less strict POR requirements, though none with only 4 bit expansion.

    Thanks,
    -Bobby

  • Thanks Bobby.

    The Power supply output is solely up to the PSU internal design rather than external load or settings. I'm afraid we'll have to live with that.

    In fact if the consequence of POR not properly set is only incorrect reg values we are okay to do some firmware fix by explicitly write all regs right after power up to make sure the value is correct.

    Just want to confirm that the chip won't be unresponsive as a result of slow power ramp? So far we have not seen any case of unresponsiveness.

    Also FYI the NXP substitution of PCA9536 doesn't call out such restriction in the datasheet.

    Thanks,
    Sandburg

  • Hey Sandburg,

    "Just want to confirm that the chip won't be unresponsive as a result of slow power ramp? So far we have not seen any case of unresponsiveness."

    Unfortunately I cannot confirm the device won't lock up like what Max has pointed out in his first post. Speaking from what I've seen is improper POR violations may cause IO expanders to sometimes start up with the wrong default bits in the registers. I have personally not seen a lock up case yet from our IO Expanders.

    "Also FYI the NXP substitution of PCA9536 doesn't call out such restriction in the datasheet."

    This was something we addressed with out new TCA line up but it seems like the PCA9536 does not have a TCA9536 variant.

    -Bobby

  • Thanks Bobby.

    Then I believe I'll have to redirect the question back to Max.   

    Hi Max,

    As both Bobby and I have only seen incorrect register values as a result of bad PoR, This doesn't seem like a coincidence. Could you please advise whether the I2C unresponsive is a real concern?

    I can understand the state machine may not get properly PoR reset but also figured there might be some sort of simple error recovery mechanism to recover the I2C / SMBus from a bad state, although the chip calls out a PoR only device.

    Thanks,
    Sandburg

  • Hi Sandburg,

    Although it may not be common, we do believe there is some risk in the device being unresponsive when powered up outside the ramp profiles defined in the datasheet. Without a reset, the initial values of the internal digital logic that implements an I2C state machine would not have well-defined values. They may take reasonable states a majority of the time or on a majority of ICs, but without a reset mechanism this could not be guaranteed in all circumstances.

    Regards,
    Max