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DS110RT410: Can't lock to 1.25GbE signal

user5316108
Prodigy 45 points
Part Number: DS110RT410
Other Parts Discussed in Thread: DS110DF410EVM

I want to lock to a 1.25g signal ,here are my register settings,I do it strictly to the mannual.

<0xff,0x04> //select cha0 register

<0x2f,0x06>//vco coarse range Ethernet

<0x36,0x31>//ref mode3

<0x60,0x00>,<0x61,0xb2>,<0x62,0x90>,<0x63,0xb3>,<0x64,0xff> //Nppm and ppm tolerance 

<0x0a,0x1c>//

<0x0a,0x10>//reset cdr 

but the cdr status 0x2 is always zero no matter what speed signal I put

Q1:why that happen,Did I miss something important to set?

Q2:I change 0x2f to 0x26 which sets the vco frequency to 10Gbps ,and I override the vco divider 0x18 to 0x30 which means 8; and i get the status to become 0xc4,but still not lock,why?

the situation really drives me mad,really appreciate your help, :-)

  • 0
    TI__Mastermind 29655 points
    Hi,

    Sorry to hear that the DS110RT410 is giving you trouble.

    The DS110RT410 should lock to a 10.3125 Gbps and 1.25 Gbps signal by default without need for register programming. It will not lock to any other signals by default unless you implement the appropriate register overrides. For what you are trying to achieve, no programming should be necessary.

    1. To help us understanding what is happening, can you please provide us some more details about your setup? Are you testing this with a DS110DF410EVM? If not, can you provide us a schematic with the DS110RT410 so that we can double-check the connections?

    2. A CDR status of 0xC4 implies that a Single Bit Transition Limit has reached, meaning that the signal that is being input to the device is potentially a subharmonic of the VCO divide-by frequency that the DS110RT410 is using to lock to the incoming signal. Can you provide us details about the source signal? Is it coming from a BERT or an arbitrary waveform generator (AWG)? If it comes from an AWG, what is the frequency you are using?

    Thanks,

    Michael
  • 0 in reply to Michael Lu (Santa Clara)
    Prodigy 45 points
    Thanks for your answer :-),
    1.I didn't use DS110DF410EVM,I use an Arm to read and write register by putting the ds110rt410 in SMbus slave mode(read_en pin tied low),and I use 25Mhz external oscillator.Since I can read the device id register 0x1 with value 0xf0,I figure there won't be much problem exists.


    2.the signal comes from a BRET ,the speed is always 1.25Gbps.the signal comes out from the light port of a BERT,then I use a PIN-TIA to transfer the light signal to voltage signal that goes into the ds110rt410 RXP0 and PXN0 AC coupled.I have tested the input signal it's properly good.

    thanks again!
  • 0 in reply to user5316108
    TI__Mastermind 29655 points

    Hi,

    Thanks for the response.

    It seems like you are reading back correctly from the DS110RT410. To make things a little simpler, please try sending in a simple 625 MHz (or in your case, a 1.25 Gbps 1T pattern) to see whether the DS110RT410 can lock to a clock pattern that operates at the 1.25 Gbps rate.

    Would you also be able to provide us with a schematic and layout of your setup?

    Also, do you have access to a DS110DF410EVM?

    Regards,

    Michael

  • 0 in reply to Michael Lu (Santa Clara)
    Prodigy 45 points

    Hi,

      Thanks for the reply, I don't have  DS110DF410EVM, and I am still confuse about the situation why the ds110rt410 can't lock to input signal automatically,here are my schematic.retimer.pdf

  • 0 in reply to user5316108
    TI__Mastermind 29655 points
    Hi,

    Thanks for the schematic. There was minimal information available in this schematic, but it seems like the connections make sense to me.

    I have another question about your setup. If you power up, send a source 1.25 Gbps signal to the DS110RT410 and do not program the retimer at all, is the DS110RT410 able to lock when you read back the CDR status?

    Regards,

    Michael
  • 0 in reply to Michael Lu (Santa Clara)
    TI__Mastermind 29655 points
    Hi,

    On a second look of the schematic, I noticed that the oscillator does not have anything connected to Pin 1. Usually this is the OE (Output Enable) pin and should be tied high for the 25 MHz signal to go to the REF_CLK input of the DS110RT410. Can you provide the part number used for device U2?

    Thanks,

    Michael
  • 0 in reply to Michael Lu (Santa Clara)
    Prodigy 45 points
    Hi,
    After a thorough check of my borad, you can't believe I have forgotten to put the loop filter connection capacitors(22nF) between those pins!
    I am sorry for my fault to cause such inconvience ! Today after I put on the 22nF cap，the chip functions totally normal.it locks to the input rapidlly!
    1.about the oscillator, it seems it's one of TXC type and pin1 is described as Enable control or NC(no conneted),so it's ok to left pin1 float.there will be still an output to the refclok pin.
    2.btw,now that I can read the eye open monitor register 0x27 (HEO)and 0x28(VEO),I don't know how to transfer these one byte value into ps and mV.(say the input signal is 1.25Gps and the voltage range is ±400mV).
    3.I also notice that the 0x28(veo) value does not equivalent to the VEO at the input signal to ds110rt410 due to CTLE gain. so how can I use this ds110rt410 to measure the VEO of the input signal ?
    Thanks for your suggestion all the time:)
  • 0 in reply to user5316108
    TI__Mastermind 29655 points

    Hi,

    I am glad that you have been able to resolve the lock issue!

    1. Thanks for confirming the functionality of the 25MHz oscillator allows you to keep Pin 1 floating.

    2. The EOM consists of a 64x64 matrix.

    To convert HEO to UI, read-back Reg 0x27 and convert from hex to decimal. Once the Reg 0x27 value has been converted to decimal, divide by 64 to obtain the HEO in UI.

    To convert VEO to mV, read-back Reg 0x28 and convert from hex to decimal. Then, reference the EOM Voltage Range in Reg 0x11[7:6] to determine the vertical step size. Multiple the Reg 0x28 value by the vertical step size to determine the VEO in mV.

    As an example, let's assume that Reg 0x27 = 0x31 and Reg 0x28 = 0xC8. Reg 0x11[7:6] = 00'b.

    HEO: Convert 0x31 to decimal (49'd). 49/64 = 0.77 UI

    VEO:  Convert 0x18 to decimal (24'd). If Reg 0x11[7:6] = 00'b, the EOM vertical range is +/-100 mV, or 200 mVpp. This means that each step is 200/64 = 3.125 mV. Therefore, the VEO is 24 x 3.125 mV = 75 mV.

    3. Unfortunately, to determine the VEO of the input signal without the CTLE, you would need a method of bypassing the CTLE within the DS110RT410. There is not a way to do this. The VEO will always be the signal after CTLE, which at minimum will still have a small amount of residual gain.

    Thanks,

    Michael