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Original question:

TLK106L: ethernet communication not stable

TLK106L: ethernet communication not stable

Ramiro Ibanez59
Prodigy 90 points
Part Number: TLK106L

Hi,

We are having the same stability problems with TLK106L Ethernet PHY as described in here :

Since we have exactly the same hardware configuration, Related to this topic we have two questions :

  1. One confusing point in the Thread is that you are talking about "XI Clock must be stable for minimum of 1 µs prior to VDD ramp." on datasheet section 4.10.1, and there in the data sheet we find only t2 definition XI clock initialization "XI Clock must be stable for minimum of 1 µs prior to configuration.".. we are also referring to the same datasheet  (SLLSEE3D –AUGUST 2013–REVISED APRIL 2016). In that datasheet there is no reference or requirement to have an stable clock before power supply. Could you clarify this issue?, is there an older datasheet with the same revision number?
  2. We have found a possible solution to it and we would like to get it confirm from TI side. We have noticed that when the chip powers up, the extended registers 0xAE (Power Back off Control register) and 0xD0 (Voltage regulator Control register) don't contain their default values. After power up they show the following values :
    1. value 0x8211 for register 0xAE
    2. value 0x0006 for register 0xD0

   With these register values the PHY is not stable on transmitting, a second receiving PHY asserts the RX_ERR signal randomly.

   To Solve this transmitting error we need to make following steps

  • Wait until reset is done (power up sequence of 300 ms).
  • Write the default values to register 0xAE (0x8020) and register 0xD0 (0x0000)
  • Trigger a Software reset, register 0x1F bit 14 (0x4000)
  • Wait 400ms
  • Start transmitting

 Following these steps after power up the link is again stable.

Could you confirm this solution? I mean, the description of these registers is limited and we are not 100% sure that will work stable.

best regards

ramiro

  • 0
    TI__Mastermind 26320 points
    Hi Ramiro,

    1. Figure 4.1 ( Power Up Timing) clearly indicates Clock is present while device supply is ramped.

    2. We recommend to follow-up the proper power up sequence as given in datasheet. Given device is characterised with this configuration, we do not ADVISE changing register configuration as it may have some other side effects you may not cover in your testing.


    Regards,
    Geet
  • 0 in reply to Geet Modi
    Prodigy 90 points
    Hi Geet,
    1 . Figure 4.1. displays clock before VDD ramping, but there is not extact timing information related to it. t1 and t2 requirements are refered to "after" VDD and reset events. How long needs to be the clock stable before VDD ramping then?
    2. We are not chaging any register values, i mean we are only setting their default values. Following your suggestion of interpreting exactly data sheet diagrams and specs, then we should be shure that Register VRCR (0x00D0) ist set to 0x0, since in its description says explicitly "must be written as 0" , right?

    Is it possible to to get from your side a TLK106L test procedure from your side, to check if our solution is valid?
  • 0 in reply to Ramiro Ibanez59
    Prodigy 90 points
    Hi Geet..
    I have just check that in DP83822 datasheet figure 1 "Power up timing" there is a clock signal active before VDD ramp, and still it was suggested to Mr Corrado (in the older thread) that he could replace TLK106L with DP83822, and both device have same power up requirements. Such solution/suggestion is not encouraging enough...
    Do you have a copy of the old TLK106L datasheet were it sets an exact requirement on XI stable before VDD ramping?
  • 0 in reply to Geet Modi
    Prodigy 90 points
    Hi Geet, Not resolved. We would like to have more information about registers VRCR and PWRBOCR.
  • 0 in reply to Ramiro Ibanez59
    TI__Mastermind 23675 points
    Hi Ramiro,

    The DP83822 is an upgrade to the TLK106L.
    TLK106L does require a stable clock at power-up.
    The VRCR and PWRBOCR registers are trimmable and the value could be different from device to device.
    We cannot share any additional information at this time.

    Like Geet mentioned, please provide a stable clock at power-up for proper operation.
  • 0 in reply to Ross Pimentel
    Prodigy 90 points

    Hi Ross,

    VRCR and PWRBOCR are Read write registers, why should be trimmed?

    Is also the data sheet concerning register description also not exact enough?

    Why is VRCR register described as "must be written as 0"?

    Is there a chance that TLK106L works fine in 80 meters long mode, and not reliable in 140 meters long mode (from registers PWRBOCR)?

  • 0 in reply to Ramiro Ibanez59
    TI__Mastermind 26320 points
    Hi Ramiro,


    1. Trimming is primarily done at factory test before shipping the parts.
    2. VRCR : If you are disabling manually, you need to right "0".
    3. It's not about 80 meters or 140 meters. Part is validated and characterised only as describe in datasheet.


    Regards,
    Geet
  • 0 in reply to Geet Modi
    Prodigy 90 points
    Hi Geet,
    sorry i am pushing so much is this way, for us is a avery important issue.

    Think that there is a ramdom error factor that could be removed by our solution. Our experience showed a huge improvement, the only error that we could appreciate was gone.

    Our solution is just :
    1. write "default values" to registers
    2. perform a software reset.

    I will give up if you confirm me that the datasheet contains wrong information concerning default register values (read/write fields).
  • 0 in reply to Ramiro Ibanez59
    TI__Mastermind 23675 points
    Hi Ramiro,

    There is a datasheet error, it should not say 'must be written to 0'.
    What you can do is write to the last 4 bits 0xF. This should resolve any issue you have.
    Can you please also send us the top marking of the components?
  • 0 in reply to Ross Pimentel
    Prodigy 90 points

    Hi Ross,

    i assume that a software reset/init is still needed after register modification.

    You get the IC top marking next week, i will be then back in the lab.

    Thanks!!!!

  • 0 in reply to Ramiro Ibanez59
    Prodigy 90 points

    Hi Ross,

    The top marking of the IC we are having problems with is :

    TLK106L

    TI 541

    ACFL G4

    regards

    ramiro

  • 0 in reply to Ramiro Ibanez59
    Prodigy 90 points
    Hi,
    Value 0xF for register 0xD0 makes the TLK106L generate too many errors on TX channel.
    We will go on with default values (given on datasheet) for registers 0xAE and 0xD0.
  • 0 in reply to Ramiro Ibanez59
    TI__Mastermind 26320 points
    Thanks. I am closing this thread. Please open a new one if you have further questions.

    Regards,
    Geet