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TCAN1051-Q1: about removing two termination resistors for less power consumption

Paul Kim
Intellectual 1430 points
Part Number: TCAN1051-Q1

Hi Team

can I get your swift reply ?

[1] VCC has blocking diode to prevent Back vias.

    my question is IC's internal power line is from [A] at Anode ?

    or is from [B] at Cathode ?

[2] CAN bus will has only two nodes for 1 pcs of master and 1 pcs of slave as below.

    the cable length will be below 30 cm.

    due to power consumption issue, I will remove two 60 ohm termination resistors.

    without considering BCI/EMC noise to be coupled onto cable, resulting that degrade signal quality,

    it is no problem to remove two termination resistors in terms of CAN PHY operation, right ?   

[3] in that case, i would like to calculate the Max ICC at Dominant stage.

    as below equation, is it ok Max 2.83mA to be estimated ?

   the Max ICC at Dominant stage   = ICC Max Normal mode(recessive) + ICC Max Normal mode(Dominant)

  = Max 2.5mA + 5V/(30Kohm/2)

  = 2.5mA + 0.33mA

  = 2.83mA

  • 0
    TI__Intellectual 2090 points

    Hi Paul,

    Thank you for your questions.  

    For [1] and [3], I will review these with the team and reply tomorrow with details.

    On [2], you should be fine to operate a point-to-point CAN bus with <30cm length.

    Best Regards,
    Max Megee

  • 0 in reply to Max Megee
    TI__Intellectual 2090 points
    Paul,

    In response to your other questions:

    The VCC diode shown in the diagram is local to the CAN driver and receiver circuits. Other nodes will be powered from Node A that you marked.

    We would expect the ICC current draw for a dominant bit on one transceiver to be around 5V/30K + 2.5mA = 2.67mA
    This has to do with the biasing scheme in the device. You will need to take account of the other node's ICC current separately.
    Currently we have not taken qualification data for this bus configuration. Also, keep in mind that the rise/fall times on the CAN bus will be significantly affected without termination resistors to aid operation.

    Please let me know if I can clarify anything further.

    Best Regards,
    Max
  • 0 in reply to Max Megee
    TI__Guru 62920 points
    Paul,

    The last point that Max M. makes above regarding operation without termination is an important one, so I want to make sure we emphasize it. CAN PHYs are designed to only drive the dominant state and become high-impedance during the recessive state. The transition from the dominant to recessive state relies on the termination resistance in order to pull the CANH and CANL lines to similar voltages. Without the termination, the CANH/CANL lines may eventually float to an acceptable recessive level, but it will take a significant amount of time (especially if there is any parasitic capacitance on the bus). This would most likely limit the usable data rate of the link to the point of being impractical.

    Max
  • 0 in reply to Miguel Robertson
    TI__Intellectual 1430 points

    Hi Max

    we will use 250Kbps, and I will check singal integrity at 250Kbps.

    BTW,, may I get your further reply ?

    [1] without two 120hom termination, you said one PHY eat 0.17mA by 5V/30K at dominant stage,

        but considering another 30Kohm on the receiver PHY, the equivelent total R would be 15Kohm(=30K/2).

        so, one PHY eat 0.33mA by 5V/30K/2 at dominant stage. right ?

    [2] our IC internally is powered from [B] I marked.

         the body diode of internal P-CH FET will block the back vias current when the PHY go to shutdown while the other PHY send dominan bit. right ?

        

  • 0 in reply to Paul Kim
    TI__Guru 62920 points
    Hi Paul,

    Sorry for the late reply. You are correct that each PHY placed in parallel on a common bus will serve to decrease the effective resistance between CANH and CANL. Note that your current calculation gives a maximum value, though - in reality the dominant-state differential output voltage is generally less than 5 V. You are also correct that back-biasing currents are blocked via the series combination of the output FETs and the blocking diodes shown on the block diagram.

    If you have further questions please just let us know.

    Regards,
    Max