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DP83849ID: ESD Protection Recommendation for POE Application

Part Number: DP83849ID
Other Parts Discussed in Thread: STRIKE

My customer is using DP83849IDVS in a POE application and they are experiencing ESD failure with the device. The design already includes TVS diodes (12KV/15KV) on the TPTDP_A, TPTDM_A, TPRDP_A, TPRDM_A, TPTDP_B, TPTDM_B, TPRDP_B, and TPRDM_B pins. What other protection recommendations do you have for this application?

  • Hi,

    Do you have a schematic you can share?
    When you say ESD failure, is it a link loss or device damage?
  • Hi Ross, 

    We shared a schematic and gerbers with Ruben, did you get them? 

    It almost looks like latch-up. We are seeing link loss and the device will heat to 75C (per the IR camera.)

    Sometimes it self recovers after a few minutes. Sometimes we have to power cycle. Sometimes we have to replace the phy. 

    It seems to happen randomly. I've left the device sitting over the weekend and come back to "link-up, link-down, link-up, link-down." I don't know if this is the same issue we've seen in ESD.

    In ESD testing we see the device occasionally heat up when shocking other (ESD-protected) GPIO on the board. But like I mentioned, we've had them fail randomly as well.


  • Hattie,

    In the previous post you mentioned that the 849 device is occasionally affected by ESD strikes to other GPIO on the board. Can you please clarify where these specific ESD strike points are in relation to the 849 on the system? For example are the GPIO on a shared supply rail with the PHY, etc.

    Also, please share the specs for your oscillator and confirm that the RBIAS resistor has 1% tolerance.

  • Hi Ross, if you can email me I'll provide the full schematic. The GPIO are generally not on a shared supply rail. They're either isolated inputs or run from another rail.

    RBIAS is 1% - ERJ-2RKF4871X
    Oscillator is ASEMB-50.000MHZ-LC-T.

    Probably another relevant point to raise - we're running off of PoE.
  • Hi Hattie,

    I just received the schematic.
    When doing testing, can you get rid of the connection to the LED pins of the PHY.
    These are not protected but also located on the RJ45. I wonder if noise is coupling into these pins.
  • We may have only shared a partial schematic with Ruben. Let me know if you need the full one.

    We have ESD diodes on the cathode of the LED - D33 and D44....TVSA04V05C006
    We have put an ESD diode from 3V3 eth to ground on a rework.

    I'll remove the R224 and and R223, but I am not optimistic!
  • Hi Ross, 

    I've checked this configuration and am still seeing occasional heating on the phy.

    What is the next step?

  • Hi Hattie,

    The breakdown and standoff voltage for those are 10V and 5V.
    This is well beyond the ABS MAX of the IO pins in the 849 datasheet.
    Please use a TVS with a standoff under our abs max and a breakdown at the abs max or below it.
  • I'll put in some lower voltage TVS on the LED lines and try that.

    What are the absolute max ratings for the TX/RX lines? Since they're biased at 3.3V, they swing up to 3.8V which is the absolute max for the device. It's tricky trying to find a TVS for these. Do you have any recommendations? Does what we have look ok?
  • Hi Hattie,

    You abs max for the IOs is Vcc +0.5V.
    If your Vcc is 3.3V then abs max is 3.8V.

    What i suggest doing first is isolate the IO from the RJ45 first to see if the damage is indeed coming from LED.
    From there we can see if the TVS on the MDI or on the IO needs to be adjusted.
  • Hi Ross,

    It *seems* like removing the resistor AND changing the TVS on the LED lines helps.
    Doing only one of these things does not seem to help, but we are still testing. Because the problem is intermittent it's hard to say for certain until we've spent quite a bit of time on it.

    It looks like the issue is with the LED. Often the first sign of a problem is the ETH_ACT_n goes low.

    I will update as we make more progress.

    I am still surprised that the abs max of the device is the same as the voltage I'm seeing on the on the TX/RX. VCC+0.5V is not much room for margin on those lines, esp since they're biased to VCC.
  • Hi Hattie,

    Yes, please keep us updated on your findings.
  • If removing the resistors does resolve the ESD issue, does this mean that we need to put ESD protection on BOTH sides of the RJ45 LEDs?

    This is not typical design practice. We already have OVP on the 3V3 rail.

  • Hi Hattie,

    Is there any way you could experiment with putting the current limiting resistor going into the PHY rather than the LED?
    This could help limit the inrush current and serve as a better means to protect the PHY.
  • It will be tough to isolate those IO from the PHY...maybe lifting the pins. we don't have any series components on those signals. We'll give it a try.
  • Hi Brian,

    Understood. If possible i suggest trying it because I do think it is odd regarding the removal of the resistor on the other side of the RJ45.
    If you have OVP on the 3V3 that should be sufficient. There might be other things at play, which is why a test with a series resistor into the PHY would be good to see.
  • Hi Ross,

    Adding an additional series resistor inline with the LED seems to help.

    I've gone back and double checked the diode drop across our LED. It's as expected 1.8V, and made sure the correct 220R was installed inline. What do you think could be going on here

    Edit to add: I've added an additional 220R by lifting the pins on the IC and putting it on the pad to the pin. The LED are still functional.

  • Hi Hattie,

    I am not sure why originally you needed both the LED and resistor to supply removed.
    However, it does make sense why adding the resistor in series to the the LED pin of the PHY improves immunity.
    IEC has high inrush current. Adding that resistor will at least help prevent a large impulse and allow for the TVS to kick in before the PHY gets damaged.

    No failures with series resistor on the PHY side, correct?