DS26LV32AT: External Biasing

Patrick Kowalczyk

Part Number: DS26LV32AT

I'm using the DS26LV32AT Quad Differential Line Receiver and want the Open Input failsafe to result in a low state when the receiver inputs are open or idle. Can an external bias in a power termination configuration be applied to the receiver input with the inverting input pulled up to Vcc and the non-inverting input pulled down to Gnd? The setup would be similar to Figure 9 of AN-903 (below) with Vcc and Gnd swapped.

over 5 years ago

0 Max Robertson over 5 years ago

TI__Guru 62910 points

Hello,

Yes, as long as the biasing network applies a differential input to the DS26LV32AT that exceeds the worst-case low-level threshold of -200 mV (between non-inverting and inverting input), then the output will remain low. In designing the biasing network, though, you should be careful to make sure that other nodes sharing the same interconnect do not apply a positive bias. This is fairly common (e.g., to establish an idle "high" level which aligns with most UART implementations), and the two different biasing circuits would contend with one another.

Max

0 Patrick Kowalczyk over 5 years ago in reply to Max Robertson

Prodigy 30 points

Thank you Max, I think this resolved my question. How much in excess of the low-level threshold would you recommend for worst-case to ensure the output remain low?

0 Max Robertson over 5 years ago in reply to Patrick Kowalczyk

TI__Guru 62910 points

Something like 10-20 mV should be sufficient. The 200 mV limit already encompasses worst-case variation due to operation at extremes of supply voltage and operating temperature, so not much additional margin would be required.

Max

0 Patrick Kowalczyk over 5 years ago in reply to Max Robertson

Prodigy 30 points

Thank you

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DS26LV32AT: External Biasing