Other Parts Discussed in Thread: TLK2201B
Hi Team,
I have some questions about TI chip: TNETE2201B (1.25Gbps Ethernet transceiver).
I want to use the TNETE2201B in an application that is not Ethernet.
I want to connect the TNETE2201B to a sub-LVDS SerDes driver that drives a proprietary protocol, which is based on a standard 8b/10b coding, at speeds up to 1.25Gbps.
The datasheet of the TNETE2201B talks about Ethernet protocols, so I want to make sure it can work with my custom interface.
Notice I only want to use the Rx path of the TNETE2201B, and I don't need its Tx path.
1) Does the clock recovery and data alignment block (or any other block) assumes an Ethernet protocol? For example, if I use my own initialization sequence which is made up of a repetitive sequence of the symbols K28.5-->K28.2-->D10.2-->D10.2-->D10.2, will they work well? (I understand the data alignment expects K28.5, which is ok because I have it in my init sequence).
2) Will the differential inputs of the TNETE2201B work with Sub-LVDS diff pair? (0.9V common mode) I have no problem with placing AC capacitors on the lines as the datasheet specifies, if this is the requirement.
3) If I choose to do so, can I work with <1.25Gbps data rates, assuming I provide a slower REF_CLK?.
4) Do you see any other reason this chip will not work with a proprietary protocol over sub-LVDS?
Thanks,
Shlomi