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SN65MLVD201: oscillation issue

Stani Bell Ngoufack Tchoufack89
Intellectual 2020 points
Part Number: SN65MLVD201

Hello,

my customer has some problem using SN65MLVD201D.

They use these components to control transfer data on a BUS ( using T-BUS of phoenix Contact of what we don’t have specification ).The first step is to have a front end with a maximum of 8 modules connected in the configuration.

Here in attached part of the schematic of the   FRONT END

Here in attached part of the schematic of other modules

Notes :

The clk+ clk- is only in one direction from front end to the modules .  The frequency now is about 25 Mhz

The tx/rx+ tx/rx- signal are in both direction controlled by some state machine in FPGA in Front end and modules .

In the front end the resistor R26 100 ohm is always enabled

In the module only the last ,  the R58 and R57 resistors ( 100 ohm ) are enabled .

They have problem of some oscillation after about 6 modules .

Do you think is necessary to add some voltage levels fixed by partition resistor on tx/rx+ tx/rx- signal preventing some strange

Level during transition from TX to RX ?

Please have a look to the schematic and tell me if there is any doubt or suggestion.

Regards,

Stani

  • TI__Genius 10250 points
    Hello Stani,

    I want to first confirm a couple of things. There are 2 separate M-LVDS buses. One for CLK which is multi-drop (one transmitter in front-end, and multiple receivers in modules) and one is for data which is multipoint (multiple transmitters and receivers). Is my understanding correct? Also, I want to confirm that the 2 terminations on each M-LVDS bus are placed on the 2 ends of each bus. So when they add modules, they need to make sure the farthest module is the one with the enabled terminations.

    Regards,
    Yaser
  • in reply to Yaser Ibrahim
    TI__Intellectual 2020 points

    Hi Yaser,

    the customer confirms that all points you asked are as you say!

    In all test that he made the termination are ok anyway he will try again to check .

    It’s very strange that when hes add the last 8 module the system crashes.

    Maybe he has a logic problem in his state machine or maybe it is a simple timing problem .

    he tried to go slow or fast and the problem still persisted.

    He made a test in only one direction for M-lvds signal and a clock is correctly recovered after 13 modules .

    Regards,

    Stani

  • in reply to Stani Bell Ngoufack Tchoufack89
    TI__Genius 10250 points
    Hi Stani,

    I agree that is a strange behavior and it could be that there is something wrong going on the protocol level, as you mentioned. Have they tried adding different modules as the 8th module, or swap the order of the modules? Again, they need to make sure only the last (farthest) module has the termination enabled. The other thing they can do next is to look at the signal integrity (eye diagram) on the LVDS bus (both CLK and Data, to compare) before they add the 8th module and after adding it.

    Regards,
    Yaser
  • in reply to Yaser Ibrahim
    TI__Genius 10250 points
    Hi Stani,

    Any update? I will close the thread and mark it as resolved for now, but please feel free to reply and the thread will get open again.

    Regards,
    Yaser
  • in reply to Yaser Ibrahim
    TI__Intellectual 2020 points

    Hi Yaser,

    the customer finally resolved the problem. Please consider this as resolved.

    Best regards,

    Stani