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SN65HVD78: SN65HVD78 Abnormal problem

Part Number: SN65HVD78

Hello Sir.

We use the SN65HVD78 device, there is a state of abnormal operation. (As shown below)

SPI_CLK_A/B signal, the converted CLK will be one less (red circle), which will cause our data transmission error.

Please help provide your suggestions to solve the problem. Thanks for kindly help~

  • AJ,

    It's abnormal to me. Usually the receiver works well with large enough input signal. What's the clock freq, 25MHz? What's the load of the receiver output? What's the state of the device? Can you plot differential voltage of the bus (A-B)? Can you check if there is any supply or ground bounding? Does the missing bit happen periodically or randomly? I'm looking forward to your feedback.

    Regards,
    Hao
  • Dear Hao.

    Good day. Please kindly reference on below. There will has some noise in the system. So need use SN65HVD78 to be converted into differential signal anti-noise. Thanks for kindly help~

    1.Usually the receiver works well with large enough input signal.

    A : Input signal is TTL 3.3V

    2.What's the clock freq, 25MHz?

    A : 12MHz

    3.What's the load of the receiver output?

    A : I am not quite sure about your question. The architecture is as shown below in SPEC.

    4.What's the state of the device?

    A : Output CLK signal abnormal. Please reference on below.

    5.Can you plot differential voltage of the bus (A-B)?

    A : Please reference on below.

    6.Can you check if there is any supply or ground bounding?

    A : Power and grounding are after isolation. I think it is ok.

    7.Does the missing bit happen periodically or randomly?

    A : Is randomly.

    Question 3

    Question 4

    Question 5

  • AJ,

    Thanks for more information. However I have more questions: 1) How many nodes on the bus? How long is the cable? Where do you probe the bus voltage? If there is more than one node on the bus, do all receiving nodes have this missing bit issue? 2) What's the voltage of ISO_SPI_1_nRE, ISO_SPI_1_DE, ISO_SPI_1_D_TX? 2) Is it possible to plot supply voltage? Where does the supply come from? 3) Would the issue go away with lower freq clock? Would the issue go away with higher resistor value of R1112/R1114? 4) What's Data loss signal? Is it how you found the issue?

    Regards,
    Hao
  • Dear Hao.

    Good day.

    Reply as follows. Thank you for kindly help~

    1. How many nodes on the bus?

    A : 4 nodes.

    2. How long is the cable?

    A : 12M.

    3. Where do you probe the bus voltage?

    A : Please reference on below.

    4. If there is more than one node on the bus, do all receiving nodes have this missing bit issue?

    A : Node 1 is master. Node 3 and Node 4 will have this problem.

    5. What's the voltage of ISO_SPI_1_nRE, ISO_SPI_1_DE, ISO_SPI_1_D_TX?

    A : I will check it.

    6. Is it possible to plot supply voltage?

    A : Please reference on below.

    7.Where does the supply come from?

    A : System 3.3V through isolator.

    8. Would the issue go away with lower freq clock?

    A : I will check it.

    9. Would the issue go away with higher resistor value of R1112/R1114?

    A : I will check it.

    10. What's Data loss signal? Is it how you found the issue?

    A : SPI transmission error. So find this problem.

    Question 3 and 4.

    Question 6

  • Dear Hao.
    Update data more information on below. Thanks for kindly help~
    1. What's the voltage of ISO_SPI_1_nRE, ISO_SPI_1_DE, ISO_SPI_1_D_TX?
    A : 3.3V
    2. Would the issue go away with lower freq clock?
    A : I wouldn’t change freq clock right now because the system need more time to calculate measurement
    3. Would the issue go away with higher resistor value of R1112/R1114?
    A : What value would you suggest? 1K or ?
  • AJ,

    What cable do you use? Is it twisted pair? Can you try using 1kOhm or higher for R1112/R1114? Do you know why the common mode oscillates around 3~4MHz? Can you check if node 2 has the same issue? If node 2 is OK but node 3/4 has errors, it might be a noise issue. If node 4 as the master, how would node1/2/3 work?

    Regards,
    Hao
  • Dear Hao.

    Good day. Please kindly reference on below.

    I would like to ask the difference signal of A in the figure below is relatively poor. But can get the CLK. The signal of B is better, but can not get CLK. What is the reason? Thanks for help~

    What cable do you use? Is it twisted pair?

    A : UL20276#28; yes it’s twisted pair.

    Can you try using 1kOhm or higher for R1112/R1114?

    A : We will try this.

    Do you know why the common mode oscillates around 3~4MHz?

    A : It might be produced by AD phase

    Can you check if node 2 has the same issue?

    A : Node 2 is OK. No this issue

    If node 2 is OK but node 3/4 has errors, it might be a noise issue. If node 4 as the master, how would node1/2/3 work?

    A : The node setting in our system is fixed, but we change another board to confirm it would be ok or not, but the result is still occur error.

  • AJ,

    When you compare the input signal with the output, You may need to take propagation of the cable into account. Usually the cable has 5ns per meter delay. For 12 meter, the delay is about 60ns. I was wondering if it's possible that the received error at B comes from the input of A.

    Regards,
    Hao
  • Dear Hao.

    Good day.

    I think it should not be a delayed problem. Provide more waveforms for your reference as below. Please provide some suggestions for help. Thank for kindly help~

  • AJ,

    One more question: does all node have the 470Ohm pull up/down resistors or does the whole bus share one 470Ohm pull up/down?

    Have you tried to use higher value resistors or remove the resistors?

    Regards,

    Hao

  • Dear Hao.
    Good day.
    All node have the 470Ohm pull up/down resistors. We will try change 470 Ohm or remove later.
    Do you thing it be related to the Common mode range? Thank for help~
  • AJ,

    Have you tried tests with larger than 470Ohm resistors? My answers from last time somehow didn't show. I will post it one more time.

    4 470Ohm in parallel makes the pull up/down equivalent to 117.5Ohm, which may make the bus load too strong therefore the voltage is attenuated. You can refer to this blog on how to calculate the equivalent resistance. The worst is the termination doesn't match the cable's impedance therefore the signal integrity is degraded.

    If node 2 can work fine, I don't think transceiver is the issue. If we make the bus signal have better quality, you might able to solve the issue.

    Regards,

    Hao