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TLK10002: The Serdes register setting of TLK10002

Part Number: TLK10002

Hi team,

My customer are using the TLK10002 in their system.

They found that their power supply 1V may have 80mVp-p, 140kHz ripple that cause the bit error in serdes.

And after they change the serdes setting(as below), the bit error has improved 

The HS_CDRFMULT from 01 = Second order. 1x mode to 02 = Second order. 2x mode

The HS_CDRTHR from 11 = Thirty two vote threshold to 10 = Sixteen vote threshold],

So the customer want to know the effect of their change, will this cause iincrease of the power consumption or if there are some other side effect of the change?

Lacey

Thanks a lot!

  • Hello Lacey,

    These setting should be fine. There shouldn't be any "side effects" or any noticeable increase in power consumption due to these settings.

    Regards,
    Yaser
  • Hi Yaser,

    Do you have some material to descript the function of the two register?

    What factor I need to consider when I set the two register?

    Why the setting of this two register matter so much when the ripple of supply is worse?

    Can you help to explain more for the two register setting?

    Lacey

    Thanks a lot!

  • Hi Lacey,

    It is hard to exactly explain how adjusting these settings help with power supply ripple. The HS_CDRFMULT and HS_CDRTHR settings adjust how the CDR tracks variations in phase (the eye pattern moving around a little). It is possible that power supply ripple is introducing phase variations.

    Regards,
    Yaser