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DS90UH940N-Q1: About the interval between FrameStart and first PacketHeader of MIPI CSI-2

Part Number: DS90UH940N-Q1

Hi,

Please tell me about MIPI CSI-2 output.

What determines the spacing between FrameStart and PacketHeader 

in the MIPI CSI-2 output of the DS90UH940N?

For example, FrameStart is output at the rising edge of Vsync (negative polarity)

input to the Serializer, and PacketHeader is output at the rising edge of the first DE.

  • Hello,

    You are correct in your assumption. At the end of the vertical sync pulse, the 940N generates the frame end and frame start packets within the vertical blanking period. On the rising edge of DE, the long packet transmission starts with the appropriate packet header. This is described in section 7.4.3 of the datasheet

    Best Regards,

    Casey