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DS90UB902Q-Q1: LOCK signal of DS90UB902Q falls to low occasionally

Kenzo Tan
Prodigy 50 points
Part Number: DS90UB902Q-Q1

Hello,

We use in combination of DS90UB901Q and DS90UB902Q.
There is a issue that the LOCK signal of DS90UB902Q falls to low occasionally and CRC errors occur(Pass signal to high).
We using Both DS90UB901Q and DS90UB902Q in Slave mode.
But I2C mode is set to pass-through.
Are there anything We should be aware of?

Regards, Ken

  • 0
    TI__Expert 5480 points

    Hi Ken, 

    Just a few things you can try first.

    1. Layout - Were proper layout guidelines in the datasheet and EVM User's Guide followed? LVCMOS Input and Output traces should be 50 Ohms single-ended for best signal integrity. Also, are you using current damping/impedance matching series resistors on these lines? Layout for the high-speed FPD-link traces (DOUT, RIN) should be 100 Ohms differential and not terminated externally(100 Ohms termination is internal to our chips).

    2. Cable Type - what cable are you using? Is it shielded? Is it automotive grade (i.e. low loss)? For shielded twin pair (STP) applications we recommended Leoni Dacar 462. How long is your cable?

    3. Schematic/General Operation - Do power supplies come up before PDB pin on both Serializer and deserializer boards? Are you operating in the correct MODE?  Looking at an eye diagram on CMLOUT will help you determine if you have an eye opening that meets the eye width and height specs listed in our datasheets. A closed eye means loss of LOCK and/or errors.




  • 0 in reply to Sally Cheung95
    Prodigy 50 points
    Hi,
    Thank you for your reply.

    1. We adopt a layout that follows the guidelines.
          The termination method is also correct.

    2. I use a twisted pair cable.
       The loss is smaller than -4 dB @ 250 MHz. (Data rate is 500Mbps)

    3. There is no problem with the power-on sequence.
        PDB is controlled after the power supply is stabilized.
        EyeDiagram output from CMLOUT is not bad. 

    LOCK signal falling and CRC errors occur once in 10 to 30 minutes.

    Do you have any other advice?
    Regards, Ken
  • 0 in reply to Kenzo Tan
    TI__Expert 5480 points

    Hi Ken, 

    Have you tried using BIST mode with it? Do you still have issues in BIST mode? 

  • 0 in reply to Sally Cheung95
    Prodigy 50 points

    Hi Sally,

    Thank you for your advices.

    I have not used BIST mode yet. I'll give it a try.
    The other thing we are trying out is the improvement of the reference clock supplied to the DS90UB901Q and the improvement of the power supply supplied by the regulator.
    Below, there are two questions.
    1) Are there any specifications for the reference clock (PCLK) input to the DS90UB901Q?
    2) For the LOCK and PASS signals output from the DS90UB902Q,
        In our case Unlock and CRC errors occur almost simultaneously.
       Generally I think that it is the order that unlocks after CRC error comes out.
       What kind of possibility is there in this case?
    Regards, Ken
  • 0 in reply to Kenzo Tan
    TI__Expert 5480 points

    Hi Ken, 

    1) For specification on PCLK, please see Recommended Serializer Timing for PCLK(1) on page 10 of the 901 D/S. PCLK is supported from 10 - 43 MHz. 
    2) Can you reword this question? I don't quite understand what you are asking.

  • 0 in reply to Sally Cheung95
    Prodigy 50 points

    Hi Sarry,

    Thank you for your reply.

    1)  There was no description about the jitter or phase noise of the reference clock.
         Please let me know if there is a required value.

    2) Sorry for confusing you.

    I think as follows.
     - CRC errors are caused by a phase shift or mismatch between the input data and the recovery clock.
     - Unlocking occurs due to the frequency shift between the input data and the recovery clock.

    Since the phase shift first occurs before the frequency shifts,
    It is understandable that a CRC error occurs first and unlocking occurs as the next step.
    However, I asked because I did not know why Unlock and CRC errors occur at the same time
    suddenly from the no error condition.

    Regards, 
    Ken

  • 0 in reply to Kenzo Tan
    TI__Expert 5480 points

    Hi Ken, 

    1.Because this is an older part, the only information I could find was on the data sheet. You may try using the auto clock feature and seeing if the lock status is stable. This may determine if the reference clock is the issue. Try the auto clock with BIST mode
    2. Perhaps the transition happens so quickly it appears simultaneous

  • 0 in reply to Sally Cheung95
    Prodigy 50 points

    Hi Sally,

    Thank you for your comments and advice.
    It will be helpful.

    Regards, Ken