TLK6002: TX FIFO overflow

Hi Piero,

Could you further describe your TLK hardware setup (e.g. data type and rate, Tx and rx settings, channel)  and provide a block diagram if possible?

Thanks,

Rodrigo Natal

HSSC Applications Engineer

• • • The schematic diagram of hardware is shown in the figure(A  channel)

      clk_out_sel = 1'b0

       refclk_0_p = 122.88M
       refclk_0_n = 1'b0
       refclk_1_p = 1'b0
       refclk_1_n = 1'b0
       TXCLK_A = 122.88M

       refclk_a_sel = 0

       refclk_b_sel = 0

       prbs_en = 0

      Send data as follows:

                                  TXDA[7:0] = tx_data[7:0]

                                  TXDA[17:10] = tx_data[15:8]

                                  TXDA[8]   = tx_k[0]

                                  TXDA[18] = tx_k[1]

                                  TXDA[9]   = 0

                                  TXDA[19] = 0

      The tx_data  is based on 16-bit data of the TXCLK_A  clock.

      tx_k[0]  contains the control bit (k-character indication) of data byte TXDA_[7:0]

      tx_k[1] contains the control bit (k-character indication) of data byte TDA_[17:10]

• LINE RATE = 2457.6M     

  SERDES PLL MULTIPLIER VALUE  = 20

  RATE SELECT = 0.5 (half)

  TXCLK_A/B = 122.88M

  REFCLKP/N = 122.88M

• The register configuration for A channel is shown below

Thanks for your setup details. I'm not immediately identifying an issue with your setup. Could you double check and confirm the following for your setup?

• Unused parallel input pins are grounded
• Double check pin configuration and settings versus datasheet section 4.18.2 "16-Bit Interface Mode (8b/10b Encoder/Decoder Enabled) (All CPRI/OBSAI Rates)". In particular, confirm the following for your setup,
  

  • Device Pin Setting(s)

    – Ensure CODEA_EN input pin is Low.

    – Ensure CODEB_EN input pin is Low.

    – Ensure RATE_A[2:0] input pins are 3’b100 (High, Low, Low) to enable software control.

    – Ensure RATE_B[2:0] input pins are 3’b100 (High, Low, Low) to enable software control.

    – Ensure PD_TRXA_N input pin is High.

    – Ensure PD_TRXB_N input pin is High.

    – Ensure PRBS_EN input pin is Low.

    – Ensure REFCLK_A_SEL input pin is Low to enable software control.

    – Ensure REFCLK_B_SEL input pin is Low to enable software control.

  •  Enable MDIO global write so that each MDIO write affects both channels to shorten provisioning time – Write 1’b1 to 0.11 GLOBAL_WRITE
  • Clock Configuration

– Select Channel A SERDES REFCLK input (Default = REFCLK_0_P/N)

• If REFCLK_0_P/N used – Write 1’b0 to 0.1 REFCLK_A_SEL

• If REFCLK_1_P/N used – Write 1’b1 to 0.1 REFCLK_A_SEL

– Select Channel B SERDES REFCLK input (Default = REFCLK_0_P/N)

• If REFCLK_0_P/N used – Write 1’b0 to 0.0 REFCLK_B_SEL

• If REFCLK_1_P/N used – Write 1’b1 to 0.0 REFCLK_B_SEL

• • Data Rate Setting - If serial data rate is 2457.60Mbps: Write 2’b01 to 1.7:6 RATE_TX[1:0], write 2’b01 to 1.5:4 RATE_RX[1:0], write 4’b1101 to 1.3:0 PLL_MULT[3:0] to select HALF rate and 20x MPY (CHANNEL_CONTROL_1 = 0x015D)

Hi:

  Did you check setup?

Regards,

Brian