Other Parts Discussed in Thread: THS8200
Currently TVP7002 is used to collect VGA signals. Due to the embedded synchronization information in TVP7002, when FPGA analyzes YUV data at present, according to the relevant information of SAV and EAV, the analyzed data has the problem of one line more than the valid line number. For example, 1280*1024@60Hz acquisition, should be normally 1024 lines, but now 1025 lines. As the board also collects HDMI signals, the YUV of HDMI and VGA come out, and FPGA uses the same set of codes. Currently, the number of HDMI signal collection lines is correct, but VGA has the problem of one more line. Please help me to see what the reason is and the solution. Thanks very much!