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DP83849IFVS-EVK: FPGA+DP83849IFVS basic product evaluation and customer demo board for fiber port network communication

Part Number: DP83849IFVS-EVK

 I used TI's demo interface board designed for DP83849.

And use the jumper to communicate with the demo board using the FPGA, and use the photoelectric conversion head (ALLRAY-a Chinese company) ATR-01105CMT/D-ST

The current debugging situation is as follows:

Both the electrical port and the fiber port management adopt the default settings. The Port A address is 00000 and the Port B address is 00001.

Electrical port:

The electrical ports of Port A and Port B are both tuned and can send and receive data normally.

Fiber port:

(The driver is the same as the electrical port)Switch the input and output signal differential line of Port B to the optical port, the FX_EN signal is pulled up, AN_1 is pulled down, and the rest are kept in the default state. After the optical fiber transceiver is connected through the optical fiber, the FPGA sends data to the PHY at a certain time interval. Now the port B's indicator lights up as follows:

The LED_LINK and LED_SPEED lights are always on, the LED_ACT light is blinking, the flashing frequency is consistent with the transmission data frequency, the photoelectric converter LINK/ACT indicator flashes, and the blinking frequency is consistent with the transmitted data frequency.

Communication situation:

No corresponding data is received on the PC side(Use wireshark capture tool and network assist),Data can be sent from the PC to the PHY and FPGA side,I am able to capture the data sent from the PC,however, FPGA side cannot receive the data sent by PC.

I use the management interface to read the values of some registers in the Port B optical port state as follows:

00H-2100H

01H-784DH

04H-0101H

05H-0000H

10H-0605H

16H-014BH

17H-0021H

18H-0000H

19H-0021H

  • Hello,

    From your description it looks like you are configuring port B to 100BASE-FX, Full-Duplex. Is this correct? Please also confirm the FPGA can operate with this mode at 100M.

    Can you clarify this "Data can be sent from the PC to the PHY and FPGA side,I am able to capture the data sent from the PC,however, FPGA side cannot receive the data sent by PC."

    Thanks,

    Vibhu

  • Hello Vibhu,

    yes,I configured portB to 100BASE-FX, Full-Duplex.And my FPGA drivers can operate with this mode at 100M.(PS: my FPGA driver can also operate with 100BASE-TX,Full-Duplex in Port B,I can transmit and receive data successfly in this mode).

    "Data can be sent from the PC to the PHY and FPGA side"means I can transmit data from my PC to DP83849 demo board,because I can capture the data which I transmit from my PC to DP83849 demo board.

    "FPGA side cannot receive the data sent by PC"means that in my FPGA program,I can not receive the data which is transmit from my PC to DP83849 demo board.

    Thanks,

    Liu

  • Hello guys,

    There are some new situations now,I did two more tests.

    Firstly,by connecting the transmit port of the Fiber Optic Transceivers to the input port, the transmitted data can be received in the FPGA.

    Secondly,using the PC to send data to the DP83849, the FPGA can receive the data sent by the PC, but the data sent by the FPGA to the PC through the DP83849 is not received on the PC.

    How can I explain this situation?

    Thanks,

    Liu

  • Hello Liu,

    Glad that the FPGA is able to receive the packets. Can you explain what you added here?

    Please compare your strap settings with section 3.4 of https://www.ti.com/lit/an/snla086b/snla086b.pdf. Table 6 outlines the required straps. This may help debug further.

    Thanks,

    Vibhu