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LMH0318: Jitter performance of re-clocked output

Part Number: LMH0318
Other Parts Discussed in Thread: LMH0395, , LMH1218EVM

Hi, I would like to understand how a previous reported issue concerning poor jitter performance on the reclocked output of the LMH0318 was resolved. The solution was not mentioned in the thread and I am experiencing a very similar issue.  In our design the data path involves using a LMH0395 cable equalizer to receive an SDI stream. Then one output of the LMH0395 feeds into an FPGA for further analysis and the second output drives a LMH0318 reclocker device to generate a re-timed output. I am using a Phabrix SXe unit to monitor the output of the LMH0318.  The Phabrix unit is measuring 0.14UI of jitter. If I reconfigure the LMH0318 to send out raw data rather than reclocked data, the jitter performance improves to 0.08UI as does the eye diagram. So it appears the reclocked data presents a worse jitter performance. Changes to register 0x03 (EQ_boost) or even trying to bypass EQ boost for 270 MHz in register 0x0D seem to have no effect.

Many thanks,

Alan.

  • Hi Alan,

    On LMH0318, there is a register - 0x99 - that controls device loop bandwidth. Default value is 0x04. Can you please change this to 0x01 and check your alignment jitter again.

    Regards,,Nasser

  • Hi Nasser,

    Thank you for your response. I have tried setting register 0x99 with the value 0x01, but observed no difference in jitter on the Phabrix unit. Below is the pseudo code of setting up the LMH0318 with the added line to change the loop bandwidth register. Can you confirm that this is how register 0x99 would be configured?

    --LMH0318 Initialization with loop BW change

    SPIWrite (0xFF, 0x04)      --Enable channel registers

    SPIWrite (0x16, 0x25)     --Enable full temperature range

    SPIWrite (0x3E, 0x00)     --Initialise CDR state machine control

    SPIWrite (0x55, 0x02)     --Initialise CDR state machine control

    SPIWrite (0x6A, 0x00)     --Initialise CDR state machine control

    SPIWrite (0x03, 0x00)     --CTLE setting. Use 00 as track is very short (EQ to Driver)

    SPIWrite (0x99, 0x01)     -- **Line add to change loop BW. Default is 0x04, suggestion is 0x01

    SPIWrite (0x0A, 0x0C)     --Assert CDR reset

    SPIWrite (0x0A, 0x00)     --De-assert CDR reset

    Also, the following code is where I add two lines to override and select raw data for out0. As mentioned, this improves jitter by using the raw data.

    --LMH0318 Initialization with raw data selected for out0

    SPIWrite (0xFF, 0x04)      --Enable channel register

    SPIWrite (0x16, 0x25)     --Enable full temperature range

    SPIWrite (0x3E, 0x00)     --Initialise CDR state machine control

    SPIWrite (0x55, 0x02)     --Initialise CDR state machine control

    SPIWrite (0x6A, 0x00)     --Initialise CDR state machine control

    SPIWrite (0x03, 0x00)     --CTLE setting. Use 00 as track is very short (EQ to Driver)

    SPIWrite (0x09, 0x20)     --Enable over-ride           ** line added to select raw data

    SPIWrite (0x1C, 0x40)     --Out0 Raw Data               ** line added to select raw data

    SPIWrite (0x0A, 0x0C)     --Assert CDR reset

    SPIWrite (0x0A, 0x00)     --De-assert CDR reset

     

    Many thanks ,

     

    Alan.

  • Hi Alan,

    I believe earlier you noted after POR your alignment jitter is within the range you need. Please do the followings after POR:

    RAW    FF     04    07

    RAW    2D    00   08   //enable manual equalization

    RAW    03     00    FF    //eq index value of 0x00 lowest EQ setting

    RAW     9B    01    FF    //reduce loop bandwidth

    RAW     0A    0C    0C   //reset CDR

    RAW    0A    00    0C     /release reset 

    Please note these are read/modify write as noted in the programming guide. Also, please make sure CDR is locked after these register settings.

    Regards,, Nasser

  • Hi Nasser,

    Again, many thanks for your reply.

    That actual problem I am addressing is that the development of the new system was performed using a calibrated Phabrix SXe and as you stated the measured jitter of 0.14UI is within spec for an SDI. So no problems and the unit passed our development tests for production release.

    However the Production test department uses a calibrated Tektronix WFM8000 unit and this unit is showing 0.39UI of jitter on the same system. In Production the system is failing the SD spec. Other example systems have been tried and all behaviour the same where they pass on the Phabrix but fail on the Tektronix. Please note this is for SD only, HD and 3G streams are fine on both.

    I wanted to see if the LMH0318 could be configured to improve jitter so that both measurement systems (the Phabrix and Tektronix) would show results within the specified range. With the reclocker set to raw data both the Phabrix and the Tektronix showed exceptional jitter performance <0.08UI.

    I was amazed to see that raw data through the LMH0318 gave such a clean eye and good jitter performance for both the Phabrix and the Tektronix. In fact the Tektronix was marginally better. But reclocked data on the Tektronix is significantly worse.

    Please note I am only using very short cable of 0.5 metres from a video test pattern generator to the Unit under test. And also 0.5 metres from the Unit under test to the Phabrix or Tek measurement unit.

    I have tried your recent posted changes without any effect. I don’t fully understand the changes, because I thought register 03 (eq index value) had no effect if register 2D[3] is cleared for manual mode.

    I know the control mechanism for the LMH0318 across the SPI interface works, as I can do things like adjust the OUT0_VOD or of course override the settings to produce raw data.

    It’s a strange problem. I would have thought I would see some difference by changing eq parameters in the LMH0318 even it makes things worse. Perhaps the use of short cables is preventing seeing any significant differences.

    I really appreciate your time and help.

    Thanks

    Alan.

  • Hi Alan,

    I am assuming for your test you are using color bar as well.

    In our lab, we use both Pahbrix and also Tek WFM8300. With Tek WFM8300 we have measured under 0.1UI of alignment jitter for SD rate.

    Do you see a difference if you change reg 0x99 from a value of 0x04 to 0x01?

    Regards,, Nasser

  • Hi Nasser,

    I am using a 100% color bars test pattern. And it is 625 so SD rates.

    Thank you for checking with the Phabrix and WFM8300.

    I don't see any difference at all in jitter or eye diagram when changing register 0x99 to 0x01.

    I am thinking that because raw data shows 0.08UI on the Phabrix and 0.07UI on the WFM then the return loss network is OK in the design.

    I see there is a TI eval module for the LMH0318. If this eval board still exists, then perhaps it would be a good approach to acquire one and perform similar tests on it. I have contacted Thileepaan (UK TI FAE) concerning the eval board. But if you have any more thoughts or ideas, then it would be very much appreciated. 

    Thanks

    Alan.

  • Hi Alan,

    You can use LMH1218EVM for this test. These two devices have the same performance.

    I was thinking about this and why there is a difference between Phabrix and Tek WFM you noted earlier. In some implementation of the FPGA at SD rate, SD rate is over-sampled for example close to 1G rate. This may lead to higher jitter. Can you please check this with another instruments beside the ones you have tested? I am thinking Tek WFM that was reporting high jitter could be over-sampling SD data rate.

    Regards,, Nasser

  • Thanks Nasser,

    I will source another instrument as suggested and perform some tests.

    Regards,

    Alan.