Other Parts Discussed in Thread: THVD1450
Hi~
May I know the data rate spec for DS36277?
Thanks and Best regards,
Tiger
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Hi Tiger,
For an analog transceiver device like this, a primary limiting factor on the data rates achievable in a system tend to be the output rise and fall times. These need to be fast enough that the output state can toggle to the opposite state within one bit period, and ideally would allow for some time for the signal to remain settled at a steady-state value. A common rule of thumb is for the signal rise/fall time to be no more than 1/3 of a data bit period. Since the DS36277's maximum output rise/fall times are 60 ns, you could consider the maximum bit rate to be (60 ns * 3)^-1 = ~5 Mbps.
Note that other factors outside the transceiver characteristics can limit the maximum data rate in the system such as the network architecture (including signal integrity impairments due to wiring stubs or capacitive loading) and the UART sampling characteristics. For example, in a J1708 application where the driver is disabled to represent one state, the time taken for the signal to transition to this state would depend heavily on the load capacitance of the network.
Please let me know if this is not clear or if you have any further questions.
Regards,
Max
Tiger,
DS36277 is a little unique in that it uses inverse logic on the DE control line. If this isn't required (for example, if the logic inversion can occur in the MCU or use an external inverter or inverting FET buffer) then we have many 3.3-V transceivers. A newer part you may want to consider here is THVD1450.
Regards,
Max