DP83867ERGZ-R-EVM: Reserved Bits Set at 1 in RO Registers

Sorry,

Those values were the wrong values from an earlier issue when we had Auto Negotiation Disabled. I meant for this register print.

STRAP_STS1    : 0x0007

STRAP_STS2    : 0x0100

CFG4          : 0x1030

BMCR_value    : 0x1140

BMSR_value    : 0x7949

PHYIDR1_value : 0x2000

PHYIDR2_value : 0xA231

ANAR_value    : 0x0DE1

ANLPAR_value  : 0x0000

ANER_value    : 0x0064

ANNPTR_value  : 0x2001

ANNPRR_value  : 0x0000

CFG1_value    : 0x0300

STS1_value    : 0x0000

REGCR         : 0x401F

ADDAR         : 0x1030

KSCR_value    : 0x3000

PHYCR_value   : 0x5048

PHYSTS_value  : 0x0002

MICR_value    : 0x0000

ISR_value     : 0x0040

CFG2_value    : 0x29C7

RECR_value    : 0x0000

BISCR_value   : 0x0000

STS2_value    : 0x0040

LEDCR1_value  : 0x6150

LEDCR2_value  : 0x4444

LEDCR3_value  : 0x0002

CFG3_value    : 0x0002

CTRL_value    : 0x0000

Hello Mark,

The reserved registers are registers that you do not need control over for configuring / debugging the PHY. Their values may still change based on the internal architecture of the PHY. I would not worry about the reserved registers for your debug.

Can you tell me more about your configuration? It looks like you are using the EVM, have you made any strap resistor changes or written to any of the registers?

What is your link partner? What mode is your link partner configured to?

BMCR [12]  = 1, indicates auto-negotiation is enabled.

PHYSTS [11] = 0, indicates auto-negotiation is enabled and has not completed

STS1 [11:10] = 00, indicates that link partner is not capable of 1000BASE-T

ANLPAR = 0x0000, indicates that link partner is not capable of 10/100

Thanks,

Vibhu

Hello Vibhu,

I work with Mark on this project. We are not using the EVM. We have a custom board which uses the Xilinx Ultrascale+ MPSoC interfaced with a DP83867E using RGMII.  I am trying to get the auto negotiation to work, but so far I have been unsuccessful and cannot get a link established. So far I only have the internal loopback test passing (up to analog loopback). We have auto negotiation currently strapped to be enabled.

I am simply trying to connect to a standard PC/laptop which also uses auto-negotiation to establish link.

The printout of register values shown in Mark's post is right after the DP83867E has been configured and is waiting for a link.

We are using Xilinx provided initialization code that is used with LWIP TCP/IP software stack.

I have executed the same test using the Xilinx ZCU102 which uses the DP83867IR, and I have confirmed that I see the same register values before successful auto-negotiation, except the reserved bits.

Thanks

Hello Mark and team,

Please try enabling mirror mode and let me know if it solves your problem. This can be done by setting 0x0031[0] = 1.

It would make sense that the registers are the same before successful auto-negotiation but I would expect the registers I mentioned above to change after.

Also if you have multiple custom boards, do you see an issue when they are linked to each other?

Thanks,

Vibhu