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XIO3130: PCIe Clock Architecture Options

Part Number: XIO3130

I am forced into a 'separate clock' architecture for my PCIe design. Is this part only compatible with a 'common clock' architecture? 

From the implementation reference guide:

"The XIO3130 is designed to meet all stated specifications when the reference clock input is within all PCI Express operating parameters."

sounds like it might, but then:

"The XIO3130 requires a 100-MHz differential reference clock. A single clock source with multiple differential clock outputs is connected to all PCI Express devices in the system. The differential connection between the clock source and each PCI Express device is point-to-point. This system implementation is referred to as a common clock design."

sounds like only common clock is valid for use with the XIO3130 switch.

I appreciate your clarification!