Other Parts Discussed in Thread: TIDM-02006
The TIDM-02006 design uses the THVD1450 with 50 MHz FSI interface to a C2000 process. The FSI interface has a clock and data line. I do not wish to calibrate the delay between clock and data for each input. What will be the worst case skew between clock and data given that the buffers will be at the same supply voltage, loading and temperature? My signal will go thorugh 1 THVD1450 configured as an Rx and 1 THVD1450 configured as a Tx.
