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TUSB544: How to adjust EQ via I2C interface

Part Number: TUSB544

 Hi team,

My customer would like to fine tune EQ value via I2c, so could you advise how to do? currently their eye diagram is not good.

They set tusb544 to "4-lane_dp" or "2-lanes_dp+usb3.1" depending on attached dp dongle.

So which registers they need to adjust? Is UTX1EQ_SEL or URX1EQ_SEL ...tec

BTW, UTX1EQ_SEL or URX1EQ_SEL are included settings of "Downstream Facing Ports" and "Upstream Facing Port"?

which bits are DFP? which bits are UFP?

for "R" and "F", what value we should to set in i2c register?


  • Paul

    1. Table 7 details the gain value for each available combination when TUSB544 is in GPIO mode. These same options are also available per channel and for upstream and downstream facing ports in I 2C mode by updating registers URX[2:1]EQ_SEL, UTX[2:1]EQ_SEL, DRX[2:1]EQ_SEL, and DTX[2:1]EQ_SEL.

    2. URX[2:1]EQ_SEL, UTX[2:1]EQ_SEL, DRX[2:1]EQ_SEL, and DTX[2:1]EQ_SEL are located in registers 0x10, 0x11, 0x20, 0x21. Please note EQ_OVERRIDE must be set to 1’b1 before the software can change the I2C EQ setting.

    3. Please refer to Table 4 for the equalization setting associated with the downstream/upstream port.



  • David,

    Thanks for reply.

    And another question is:

    The table 7 only described how to control equalization by gpio,

    but it doesn't describe what i2c registers values we should to set for specific EQ GAIN.

     For example, DISPLAYPORT_2 Register,

    it has 4bit for UTX1EQ_SEL and 4 bit for URX1EQ_SEL,

    how to map the bits to the Table 7?


  • Paul

    The first row in Table 7 starts with EQ setting of 0 all the way down to EQ setting of 15. 

    So for example if you write 0 to the registers, it would corresponding to this