TCA9539-Q1: [J52/J53] GPIO expander functionality question

Kyle Chang1 said:

Part Number: TCA9539-Q1

Hi Receiver,

Aim to GPIO expander, there are some questions be raised by client in FuSa meeting below and pls. help to redirect correct contact window if need.

 

Per DS mentioned, each 8-bit port is read independently, the interrupt caused by port 0 is not cleared by a read of port 1, or vice versa.

[Bobby]

You are missing the other part: "Resetting the interrupt circuit is achieved when data on the port is changed to the original
setting"

This means that the INT can de-assert/reset itself if the input that changed states (caused the INT to assert) were to change back to its original state. This means the INT does not latch itself low if an input changes states and goes back. I'm guessing what ever problem your seeing is due to the fact that the INT doesn't latch and the GPI that caused the INT could be missed if you don't read the register quick enough.

Given above statement, it showed me only correct port which interrupt be triggered be read by master then the interrupt flag just can be cleaned.

Nevertheless, this method just existing when the GPIO expander is functioning properly, may we learn some unexpecting/corner case  below?

 

1. Is it possible for the GPIO expander to fail such that it doesn’t provide an interrupt when requested?
   [Bobby] I have yet to see a case like this other than if the device was damaged.
2. Continues above, if so, can any mechanism inside GPIO expander to detect this fail and report to master?
   [Bobby] No.
3. If more than one IO ports changed status at the same time (or within the time between one I2C message and the next), do they all get reported when the next I2C message is generated or is there any chance one may be missed?  How does the interrupt and clear work in this case?
   [Bobby] There is a window where if an input changes close to the ACK pulse during a read, it could be missed: "Interrupts that occur during the ACK clock pulse can be lost (or be very short) because of the resetting of the interrupt during this pulse" If the window is between the I2C messages (between a stop and start condition) then an INT shouldn't be missed.
4. Last but not least, are there ANY failure modes that would cause the GPIO expander to function abnormally?
   [Bobby] For the TCA family, there is not a known issue/failure state where the INT is missed or a GPI is not reported correctly.

BR,

well noted and appreciate your input, Bobby.

if so, the INT can be cleared by either beyond master reading or port state change to original setting. It seems to me the OR mechanism to assert the INT, right?

With regard to item 3, can you guide me where to figure out the ACK pulse during a read, is 3.45us tvd(ack) be addressed in page6 or something else?

BR,

Kyle Chang1 said:

well noted and appreciate your input, Bobby.

if so, the INT can be cleared by either beyond master reading or port state change to original setting. It seems to me the OR mechanism to assert the INT, right?

[Bobby] The logic can actually be seen in the simplified diagram on figure 24:

The 'current/remembered' state and the present state of the GPI is compared through a NOR circuit. An ACK pulse can shift the flip-flop's Q output to the 'present' state and store that value as the new 'current/remembered' state to compare to the state on the GPI pin.

With regard to item 3, can you guide me where to figure out the ACK pulse during a read, is 3.45us tvd(ack) be addressed in page6 or something else?

 [Bobby] In Figure 20 above, this ACK pulse is fed to that clock input of the flip-flop earlier to store the new value. If a state changes on the GPI of that particular port were to change close to that rising edge on the ACK, the INT could remain de-asserted since the change stored the new GPI state as the 'remembered state'

BR,

Thanks for your guiding on functional block diagram, Bobby.

Nevertheless, the logic symbol shows to me should XOR gate a bit confused with NOR gate you mentioned in the statement.

In further, per previous explaining, the "read pulse" is on purpose to clear the "INT" (back to high). If so, the logic gate supposed to be "XNOR" to supersede XOR or NOR and reasons below depiction.

Pls. kindly correct me if there is any misunderstanding.

As to item3 you posted, given the depiction, the Data 2 and Data 3 were both missed in the I2C reading, does it mean the state change on the input port need to remain sufficient time till next ACK available?

BR, 

Hi Bobby,

Is there any workaround can prevent below issue? The ACK clock pulse could be 10us for I2C standard mode and 2.5us for fast mode, right?

"Interrupts that occur during the ACK clock pulse can be lost (or be very short) because of the resetting of the interrupt during this pulse. "

BR

Paddy

Hi Bobby,

May I learn there is any updated?

BR,

Hi Bobby,

Can you please provide failure rate for fault tree analysis?

BR

Paddy

Hi Paddy,

Are you referring to a Functional Safety FIT Rate, FMD and Pin FMA document?

Also, are you from the same company as the original poster? I think to send the document I would need to send it to the field application engineers assigned to your account. I have a document in a draft phase for this device but don't think I can share it here.

Thanks,

-Bobby

Hi Bobby

Yes, I am referring to Functional Safety FIT Rate, FMD and Pin FMA document.

Yes, we are in same company.

Not sure who is assigned to my account.

Can you please send those data to him/her and let me know his/her name?

BR

Paddy|

Hi Paddy,

The FAE on your account is Lynn, and Allen/Jazz.

I am working on the draft for the document. My manager will proofread the document by Friday and I will submit it to be generated sometime next week.

I have messaged Lynn and she said she will reach out to you sometime next week.

Thanks,

-Bobby

Thank you Bobby.