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SN65HVD62: question about Receiver duty cycle spec

Part Number: SN65HVD62

Hi team,

Our customer has a question about the receiver duty cycle spec in datasheet.

As shown below, when bitrate is 115.2kbps,the error of duty cycle reaches 10%

But according to the AISG3.0 rules:duty cycle  of a single modem is 5% as shown below:

So is the IC not accord with the rules? and how do we consider the spec of  the duty cycle when designing the chip?

  • Dane,

    If you look at the duty cycle of RX, the spec @ 115.2kpbs on the datasheet is a little beyond the AISG limit. However in the real applications, the temperature, supply, and input voltage may not vary as much as stated on the datasheet. So usually the measurement result is better. Another point is that what matters more is the cascaded duty cycle in system design.

    Regards,

    Hao