Hi team,
Our customer has a question about the receiver duty cycle spec in datasheet.
As shown below, when bitrate is 115.2kbps,the error of duty cycle reaches 10%
But according to the AISG3.0 rules:duty cycle of a single modem is 5% as shown below:
So is the IC not accord with the rules? and how do we consider the spec of the duty cycle when designing the chip?