Other Parts Discussed in Thread: DS15EA101,
Hi,
I would like to buffer a 1 Gbps single ended 1.2V signal over an FMC cable to an FPGA, I'm wondering if there would be any problems with directly connecting the single ended input to Vpos and a constant 0.6V to Vneg. This would cause the input Vcm to swing 300mV to 900mV, and I'm concerned about that noise showing up at the output and how severe it may be. Also, I'm wondering if after the 100 Ohm differential termination, the inputs to the rest of the diff amp are high impedance? If I connect a 0.6V constant source to Vneg I'll need to take that source resistance into account when terminating Vpos.
Thanks,
Jack