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TUSB522P: Question about Impedance when using TUSB522p

Part Number: TUSB522P

Hi, I am going to use TUSB522p in the FPCB connecting between main board and USB Device.

Then I thought USB SSTX, SSRX lines should be on the top or bottom of layer as written in datasheet's guideline,


but, our cad team said to meet 90 ohm impedance lines, then SSTX, SSRX lines should be 2nd or 3rd layer of the pcb.


If I route these SSTX, SSRX in the 2nd or 3rd layer, then I should use several vias which will violate TI's layout guide line.


Below is layout guide of TI's. 

What is the best way in this situation?

1. Impedance 90 ohm is more important? -> Then SSTX, SSRX will routed in 2nd or 3rd layer and use several vias.

2. High Speed lines should be Top or bottom routed.-> Then SSTX, SSRX can not meet 90 ohm impedance.  

  • Hi,

    It is important to keep the trace impedance at 90 ohm +/- 10%. This is not always possible on top and bottom layer due the to board stack up and other factors. The number of vias should be minimized. Ideally you would use no more than 2 sets of vias (entry and exit to/from mid layer).  When routing on mid-layers you should consider the use of micro-vias. Through all vias create stubs when used in cases like this (via copper from layer 3 to bottom not used). Stubs can impact the overall channel impedance as well and create reflection/distortion in the data. 

    There are other options for minimizing the effect of vias on the data path You can also review the document below as it has many useful tips for high speed layout:


  • Thanks, Malik. Great help to me.