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DS110DF111EVM: Clock data recovery lock problem

CHEVALLOT Mickael
Prodigy 100 points
Part Number: DS110DF111EVM
Other Parts Discussed in Thread: DS110DF111, LMX2595, LMX2595EVM, DS110DF410EVM

Hello,

I'm using a DS110DF111 evaluation board to generate PRBS signal on a 1 GHz input signal.

The input signal is generated using a LMX2595 evaluation board.

I'm using the same 25MHz reference clock for both boards.

Unfortunately, the CDR of the DS110DF111 device can't achieve to be locked, even if I manually specify the frequency of the input signal.

Do you have any information that should solve my problem ?

Per advance thank you

Mickael

  • 0
    TI__Mastermind 18911 points

    Hi Mickael,

    Do you have the ability to generate a 1.25 GHz input signal from the LMX2595 evaluation board instead of 1 GHz?

    The DS110DF111 can lock to subrates that are related to a data rate between 8.5 - 11.3 Gbps by a multiple of 1,2,4,8.  Relating a 1 GHz input signal to a data rate by a factor of 8 would yield 8 Gbps, which is outside of the data rates supported by the DS110DF111.

    In order to verify that you can achieve CDR lock and generate a PRBS signal, I would recommend using an input signal of 1.25 GHz or 10.3125 GHz since these are the data rates that the DS10DF111 expects with the default configuration.  After you have verified that you can achieve CDR lock and generate a PRBS signal at this data rate, then change the input signal frequency to a subrate of your desired PRBS data rate and adjust settings on the DS110DF111 to accommodate this.

    Regards,

    Drew Miller

    HSSC Applications Engineer

  • 0 in reply to Drew Miller1
    Prodigy 100 points

    Hi Drew,

    I have sent a 1.25GHz input signal to the DS110DF111 device. It detects the input signal but, unfortunately, it's not locked :

    The 1.25GHz input signal was generated using LMX2595EVM  :

    Have you an idea of the problem ?

    Per advance thank you

    Best regards

    Mickael

  • 0 in reply to CHEVALLOT Mickael
    TI__Mastermind 18911 points

    Hi Mickael,

    In SigCon Architect, please select "Ethernet" from the "Standard Data Rate Selection" section.  After this, select "Apply to All Channels", then "Reset CDR All Channels".

    Please let me know if you are able to achieve CDR lock by doing this.

    Thanks,

    Drew Miller

    HSSC Applications Engineer

  • 0 in reply to Drew Miller1
    Prodigy 100 points

    Hi Drew,

    Thanks for your support.

    I've done your proposed configuration.

    Unfortunately it's not locked.

    If I select Enable Manual EQ Boosting and Boost 3 Limiting bit, it changes behavior on the DS110DF111 : on the status page, I obtain these successive states :

    and

    Does it means that the input frequency is not accurate enough ?

    Per advance thank you

    Best regards

    Mickael

  • 0 in reply to CHEVALLOT Mickael
    TI__Mastermind 18911 points

    Hi Mickael,

    I made a mistake in one of my earlier responses.  When the retimer is expecting a 1.25Gbaud signal, the corresponding clock signal should actually be 1/2 of that, 625 MHz.  I apologize for any inconvenience this may have caused.

    In lab today I intended to reproduce your setup, but could not get access to a DS110DF111.  I gained access to a similar component (DS110DF410EVM) and was able to achieve CDR lock using a 1.25GHz input signal by selecting "Infiniband" as a standard data rate.  This worked because the infiniband data rate setting expects the symbol rate to be related to 10Gbaud by a divider of 1,2, or 4.  A 1.25GHz clock signal corresponds to a 2.5Gbaud signal.  This matches with 10Gbaud/4.  I was able to achieve CDR lock using default CTLE settings (Adaptive Mode 1, CTLE only).

    Please follow my previous response but select "Infiniband" instead of "Ethernet".

    Thanks,

    Drew Miller

    HSSC Applications Engineer

  • 0 in reply to Drew Miller1
    Prodigy 100 points

    Hi Drew,

    It works !

    Thank you so much for your help

    Best regards

    Mickael