Hello everyone
we a trying to forward a gigabit link using the DS100DF410. The setup is FPGA -> DS100DF410 -> RJ45 -> RJ45 -> DS100DF410 -> FPGA. At a later point we would like to cascade more than 2 of the DS100DF410 to forward data directly in the HW.
I have already read the available posts where it is said to bypass the CDR and change the MUX settings by doing this (
):
Reg 0xFF = 0x0C //Access channel registers
Reg 0x2F[7:4] = 1100'b // Set lock rate for Interlaaken-2 (10.3125 Gbps with Divide-by-1 VCO divider only)
Reg 0x1E[7:5] = 000'b // Output raw data if CDR is not locked
Reg 0x3F[7] = 1'b //This is a reserved bit that must be set to ensure appropriate raw data is output
I did this but the problem is that we get the raw data which is not acceptable for us.
Another user has spoken about register 0x3F Bit 7 (not documented), is it required to write this bit?
So is there any chance to get a retimed 1G stream out of the DS100DF410? And if yes then please list the required register settings (device is in SMB slave mode). The datasheet seems to be inconsistent (e.g. Register 0x2F where the rates are defined but not described).
A reference oscillator 25MHz is available.
Regards
Valentin
