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TCA9539-Q1: trigger signal for INT pin

Part Number: TCA9539-Q1
Other Parts Discussed in Thread: SN74LVC1G80-Q1, , SN74HCS74-Q1

Dear team,

According to below description, INT pin will be low when input signal has rising or falling edge. My customer hopes that INT pin only be triggered by rising edge, and they don't allow falling trigger. Is this feasible? 

Thanks & Best Regards,

Sherry

  • This device is designed to signal any change with an interrupt.

    To get an interrupt only on rising edges, put a SN74LVC1G80-Q1 configured as a frequency divider (Q connected to D) in front of the input.

  • Sherry,

    Our I2C I/O expanders like the TCA9539-Q1 are designed to trigger an interrupt when the status of an input changes, which is why the section you have highlighted mentions rising or falling edges. The interrupt output is triggered when the state changes, but released if all inputs to the device return to their original states before being read. A flip-flop like the aforementioned SN74LVC1G80-Q1 would allow you to only receive input status changes on rising edges, but you would not be able to read the exact status of the original signal since this would no longer be connected to the I/O expander and its falling edges would not be propagated. This may or may not be a concern based on your customer's application.

    Best,

    Danny

  • Hi  Danny,

    Thanks for you reply!

    I don't understand what is the difference between point A and point B when I/O pin is set as input. The point A is current  sampled value and the point B is last sampled value, right?

    For example, the input series is 1->0->1->0, then point A is 1->0->1->0 and point B is default value(0?)->1->0->1, so INT pin is (1 XOR default value)->1->1->1, right?

    Thanks & Best Regards,

    Sherry

  • Point A is not "sampled"; it is read continuously. Point B is the sample at the last time the port was actually read.

    Point A changes whenever the input pin changes. Point B can change only when the port is actually read.

  • Hi Ladisch,

    Thanks for your reply! If we design as below, and I/O pin is input mode. We must connect D to a GPIO to initial D pin, right? Because I/O pin is Hi-Z state.

    Thanks & Best Regards,

    Sherry

  • Hi Ladisch,

    If I don't read the input register, point B won't change, right? But in this way, INT pin doesn't work. Point A is 10110, but point B keeps 0 due to no read pulse, then INT will output wrong trigger.

    Thanks & Best Regards,

    Sherry

  • The circuit above does not need initialization. The initial state of D is random, but you do not care about its actual value, only about changes.

    When two rising edges happen without a read between them, the flip-flop toggles back to its initial state, and the interrupt will be lost.

    If you cannot guarantee that the I²C master does the reads fast enough, then you have to use a more complex circuit: Use the SN74HCS74-Q1, initialize it to 0 by pulling CLR low with a GPIO output, and connect D to VCC so that any rising edge results in the output going to 1. If any further rising edges happen, Q will stay high. Clear it again with CLR only after you have handled the interrupt. (You then have to do another read because clearing the flip-flop raised another interrupt.)

  • Hi Ladisch,

    My customer decides to use this architecture D type flip-flop+TCA9539-Q1 to achieve single edge trigger function. But we still have some questions,

    1. Is it necessary to add a 10kohm resistor between D pin and Q pin? What is the resistor's function?

    2. Does D pin and Q pin need pullup or pulldown resistors? When this device powers up, what is the Q pin state? High level, low level or Hi-z state? If Q is Hi-z state, and D pin is floating, then how do they change to high level or low level?

    3. What is this device's quiescent current, Icc? But Below two pictures shows different Icc value, I am not sure which one is the Iq.

    4. You said that If we cannot guarantee that the I²C master does the reads fast enough, then we have to use a more complex circuit. I don't understand this. What does I2C speed affect? I only cares about rising edge, and I don't need the falling edge.

    Thanks & Best Regards,

    Sherry

  • 1. The 10 kΩ would be needed if you wanted to initialize the flip-flop to a known state (by using the GPIO as an output). This is not necessary.

    2. The initial state of a flip-flop is unknown. Pull-ups or pull-downs cannot change that; it would require separate set/clear inputs.

    3. ICC is approximately zero. That graph is for input voltages that violate the VIL/VIH limits (see [FAQ] How does a slow or floating input affect a CMOS device?).

    4. I was not talking about the speed of the I²C bus itself, but whether the master is always able to read the interrupt status before the next rising edge can happen. This depends on the minimal time between two edges, and on the master's firmware.