DS110DF111: two questions on ds110df111

Hi Team,

Correct on mistake, change 0x54 to 0x07.

BR

brandon

Hi Brandon,

I have a few questions in regards to your first item.

- The signal detect bit is in CHAN_REG 0x54. Can you confirm that you were reading this and not 0x51?

- What is the estimated channel loss between the 10G SFI/XFI sources and the DS110DF111.

In regards to your second item:

Yes, setting SHARED_REG 0x07 does configure the loopback function.  The input signal has CDR and CTLE processing prior to being looped back.  Because of this, the retimer configuration CDR and CTLE does affect the loopback signal.  Figure 6 in the DS110DF111 datasheet clarifies this.

Thanks,

Drew Miller

HSSC Applications Engineer

Hi Miller,

some new date coming from latest test:

For now, we have two 10GE XFI under testing:

Port A could normally work with Loopback , and when set 0x07, could also link-up normally;

Port B could not link-up when set 0x07;

if we check the register, we could find that:

Port_B retimer: reg_0x54==0x80  signal detect

                         reg_0x2==0x0  CDR Not Lock

Port_A retimer:reg_0x54==0x80  signal detect

                         reg_0x2 bit [5:3]==0x011  CDR Lock

also some tests result below:

1. Port_b CPU-MAC PCS Loopback could work normally;

2.Port_b Tx Fly line to RX could link-up normally;

3.Dump and compare the two retimer log, it seems have the same register value

The attached picture is the all channel register dump of the corresponding input ports of the two retimers. The marked channel 0 is the normal channel, and the channel 4 corresponds to the abnormal channel. See if you can get more useful information.

BR

Brandon.

Hi Brandon,

Thanks for the register dump.  I am looking into this and will get back to you with more details tomorrow.

Thanks,

Drew Miller

HSSC Applications Engineer

Hi Brandon,

Looking over the registers of your bad channel, we can see that register 0x52=0xA5. This register contains the CTLE boost value and is very high.  I have two debug options.  Please try option #1 first and if it does not work, then try option #2.

1) Manually force CTLE = 0x00

Please make the following register writes to the bad channel.  The goal of this step is to reduce any over equalization that is occurring.

2) Enable DWDM Mode

This is another step that can be taken to reduce CTLE EQ boost.  This step is only recommended if option #1 fails.

Please note that in both of the procedures above, you will need to select the appropriate channel register prior to making these writes.

Thanks,

Drew Miller

HSSC Applications Engineer