Could you help check the SN75LVPE4410 schematic as below and any need to adjust
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Please note some comments below:
1). Normally PCIe TX already has AC coupling Caps. So you may not need Caps such as C70 on input of the LVPE4410.
2). TX AC coupling Caps such as C69 are normally in order of 220pF.
3). It would be a good idea to provide a ferrite bead on V3.3S - instead of R100.
4). PWDN1 and PWDN2 go to a jumper/header. It would be a good idea to connect this pin to PERST# - after inversion. This will synchronizes CPU and the end point.
5). Your schematic shows RX_DET at L3 - TX detection disabled. In PCIe applications, it maybe preferred to have this pin floating(auto RX detect).
6). Your EQ index is at level 5. It would be a good idea to start with index 0 and then increase as needed. This would provide a much better linearity.
7). To provide optimum linearity it is best to have GAIN and VOD floating - this would provide 0dB DC gain and 1:1 VOD linearity.