SN65HVD233-Q1: Dominent and recessive current for full load

Hi Monisha,

The current specifications on the datasheet describe the current consumed by the transceiver itself during its different passive or driving states, and indeed does not specify the actual current passing through the supply pin to drive the bus. This extra current will depend heavily on the load on the system bus and the contents of the data being sent (%dominant). The output current during the dominant state can be estimated using the graph in Figure 11 if the system expects to have a 60-ohm load (typically two 120-ohm termination resistors in parallel). If some other load is used, this current can be estimated by calculating the current through the load when the differential output voltage (VOD) is at its typical value (2.0V). For example, with a load of 60-ohms and output voltage of 2.0V, the dominant current would be around 33mA. This rough estimate is close to (slightly worse) that which is shown in Figure 11 for these conditions. 

The amount of time that the data through the network keeps the signal dominant will also have a large impact on overall power usage. Because recessive levels (logic 1s) are passively driven, they consume negligible current when compared to the dominant (logic 0) state. This calculation is pretty straight forward to estimate, because you can simply multiply your estimated dominant current by the percentage of time the bus is expected to be in this state. This estimation does ignore the small amount of biasing current needed for the recessive state, so if you expect the bus to be recessive most of the time, it may be good to include this in a more complex estimate. 

Let me know if this makes sense and if you have any questions.

Regards,
Eric Schott