• State
  • Locked Locked
  • Replies 9 replies
  • Subscribers 32 subscribers
  • Views 471 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DP83849IF: Connecting to an AFBR5803-ATZ fibre transceiver. 100BASE-FX

jean-michel
Prodigy 10 points
Part Number: DP83849IF

Hi,

I'm trying to connect a DP83849IF to an HFBR5803ATZ. I have used the schematics fig 8.2 of the DD83849-IF data sheet. This doesn't work.

I think understanding the design of the DP83849IF PMD interface is key to solving this problem.

Has anyone tried this? Are the level used LVPECL? Why not using a capacitive coupling on the receive side as well as on the transmit side?

Shouldn't the 130R and 80R resistors inverted depending on the location (output or input)?

Thanks

  • 0
    TI__Genius 16030 points

    Hello,

    Application diagram in datasheet is correct and in use widely. I could not find the datasheet of the SFP you are using. Can you check if it supports 100mbps corresponding to 100BaseFx standard?

    --

    Regards,

    Vikram

  • 0
    Prodigy 10 points

    Hi Vikram,

    The part I use is the AFBR-5803ATZ from Broadcom, (there is a typo in my problem description where it says HFBR-2803ATZ).

    It says: Full compatibility with the optical performance requirements of 100BASE-FX version of IEEE802.3u.

    Thanks

  • 0 in reply to jean-michel
    TI__Genius 16030 points

    Hi,

    Do you see FX_EN = 1 in register 16h? Is correct mode selected on both side : full-duplex/half-duplex? To rule out link-partner issue, may be you can try linking up two boards of 849.

    --

    Regards,

    Vikram

  • 0 in reply to Vikram Sharma
    Prodigy 10 points

    Hi Vikram, Yes we think the register is configured correctly. Please see file attached. I also reattached the schematic we use. ThanksTI investigation.pdf register.pdf

  • 0 in reply to jean-michel
    Prodigy 10 points

    Hi Vikram,

    I am afraid we are getting nowhere with this. We really need help.

    To re-cap our application.

    We are using the DP83849IF to provide the ability for our product to connect to either UTP Ethernet or Optical FX. See diagram below.

    This is the circuit diagram...

    We have the Copper (UTP) connection working but so far are unable to get the Optical interface working.

    Please can you double-check that the interface between the Broadcom AFBR5803-ATZ and the DP83849IF is correct.

    Also, is enabling the optical as simple setting the FX_EN bit (bit 6) in the PCSR (address 16h) or are there other bits I need to set/clear etc...

    Please take a look at the two sets of registers below.

    Our plan is to examine the state of a DIP switch at power-up and set which interface we route the the microcontroller MAC.

    Any hints, tips or clues you might have would be appreciated.

    Many thanks in advance

    Jean-Michel

    Any hints

  • 0 in reply to jean-michel
    TI__Genius 16030 points

    Hello Jean,

    Thanks for sharing the registers. From register log, I can see that fiber side is linking up fine with link-partner and the problem is somewhere on PHY - MAC interface. I have put some comments on the attached register logs and a possible setting to try.

    --

    Regards,

    Vikram2477.register.pdf

  • 0 in reply to Vikram Sharma
    Prodigy 10 points

    Hi Vikram, 

    I did as you requested but still have problems.

    I think the situation has improved a little because the media converter I am using to communicate with the target board now has flashing link LEDs on it.  However, I still have no comms.  Something must still be wrong.

    I have captured all of the optical phy's registers again and broken them down for you. Please can you take a look and double-check the register contents for me in case I have something else I need to do.

    I am sorry but I am unable to post a file so have pasted a table....I hope you can read it OK.

    Thanks again Jean-Michel.

    Register Address REG NAME PHYOptical_REG
    [Addr = 1]    		 PHYOptical_REG
    [Addr = 1]    		 Comment
    0 0h BMCR  0x2100 Bit 00 RESERVED 0 X
    Bit 01 0
    Bit 2 0
    Bit 3 0
    Bit 4 0
    Bit 5 0
    Bit 6 0
    Bit 7 COLLISION TEST 0 0 = Normal Operation
    Bit 8 DUPLEX MODE 1 1 = Full duplex Operation
    Bit 9 RESTART AUTO NEGOTIATION 0 0 = Normal Operation
    Bit 10 ISOLATE 0 0 = Normal Operation
    Bit 11 POWER DOWN 0 0 = Normal Operation
    Bit 12 AUTO NEGOTIATE ENABLE 0 0 = Auto-Negotiation Disabled - bits 8 and 13 determine the port speed and duplex mode.
    Bit 13 SPEED SELECTION 1 1 = 100 Mb/s.
    Bit 14 LOOPBACK 0 0 = Normal Operation
    Bit 15 RESET 0 0 = Normal Operation
    1 1h BMSR  0x784D Bit 0 EXTENDED CAPABILITY 1 1 = Extended register capabilities
    Bit 1 JABBER DETECT 0 0 = No Jabber.
    Bit 2 LINK STATUS 1 1 = Valid link established
    Bit 3 AUTO-NEGOTIATION ABILITY 1 1 = Device is able to perform Auto-Negotiation.
    Bit 4 REMOTE FAULT 0 0 = No remote fault condition detected.
    Bit 5 AUTO-NEGOTIATION COMPLETE 0 0 = Auto-Negotiation process not complete.
    Bit 6 MF PREAMBLE SUPPRESSION 1 1 = Device able to perform management transaction with preamble suppressed, 32-bits of preamble needed only once after reset, invalid opcode or invalid turnaround.
    Bit 7 RESERVED 0 X
    Bit 8 0
    Bit 9 0
    Bit 10 0
    Bit 11 10 BASE-T HALF DUPLEX 1 1 = Device able to perform 10BASE-T in half duplex mode.
    Bit 12 10BASE-T FULL DUPLEX 1 1 = Device able to perform 10BASE-T in full duplex mode.
    Bit 13 100BASE-TX HALF DUPLEX 1 1 = Device able to perform 100BASE-TX in half duplex mode.
    Bit 14 100BASE-TX FULL DUPLEX 1 1 = Device able to perform 100BASE-TX in full duplex mode.
    Bit 15 100BASE-T4 0 0 = Device not able to perform 100BASE-T4 mode.
    2 2h PHYIDR1  0x2000 Bit 0 OUI_MSB 0 OUI Most Significant Bits
    Bit 1 0
    Bit 2 0
    Bit 3 0
    Bit 4 0
    Bit 5 0
    Bit 6 0
    Bit 7 0
    Bit 8 0
    Bit 9 0
    Bit 10 0
    Bit 11 0
    Bit 12 0
    Bit 13 0
    Bit 14 1
    Bit 15 0
    3 3h PHYIDR2  0x5CA2 Bit 0 MDL_REV 0 Model Revision Number
    Bit 1 1
    Bit 2 0
    Bit 3 0
    Bit 4 VNDR_MDL 0 Vendor Model Number
    Bit 5 1
    Bit 6 0
    Bit 7 1
    Bit 8 0
    Bit 9 0
    Bit 10 OUI_LSB 1 OUI Least Significant Bits
    Bit 11 1
    Bit 12 1
    Bit 13 0
    Bit 14 1
    Bit 15 0
    4 4h ANAR  0x0DE1 Bit 0 SELECTOR 1 device supports IEEE 802.3u
    Bit 1 0
    Bit 2 0
    Bit 3 0
    Bit 4 0
    Bit 5 10 1 1 = 10BASE-T is supported by the local device.
    Bit 6 10_FD 1 1 = 10BASE-T Full Duplex is supported by the local device.
    Bit 7 TX 1 1 = 100BASE-TX is supported by the local device.
    Bit 8 TX_FD 1 1 = 100BASE-TX Full Duplex is supported by the local device.
    Bit 9 T4 0 0 = 100BASE-T4 not supported.
    Bit 10 PAUSE 1 1 = Advertise that the DTE (MAC) has implemented both the optional MAC control sublayer and the pause function as specified in clause 31 and annex 31B of 802.3u.
    Bit 11 ASM_DIR 1 1 = Advertise that the DTE (MAC) has implemented both the optional MAC control sublayer and the pause function as specified in clause 31 and annex 31B of 802.3u.
    Bit 12 RESERVED 0 X
    Bit 13 RF 0 0 = No Remote Fault detected.
    Bit 14 RESERVED 0 X
    Bit 15 NP 0 0 = Next Page Transfer not desired.
    5 5h ANLPAR  0x0000 Bit 0 SELECTOR 0 Protocol Selection Bits
    Bit 1 0
    Bit 2 0
    Bit 3 0
    Bit 4 0
    Bit 5 10 0 0 = 10BASE-T not supported by the Link Partner.
    Bit 6 10_FD 0 0 = 10BASE-T Full Duplex not supported by the Link Partner.
    Bit 7 TX 0 0 = 100BASE-TX not supported by the Link Partner.
    Bit 8 TX_FD 0 0 = 100BASE-TX Full Duplex not supported by the Link Partner.
    Bit 9 T4 0 0 = 100BASE-T4 not supported by the Link Partner.
    Bit 10 PAUSE 0 0 = Pause function is not supported by the Link Partner.
    Bit 11 ASM_DIR 0 0 = Asymmetric pause is not supported by the Link Partner.
    Bit 12 RESERVED 0 X
    Bit 13 RF 0 0 = No Remote Fault indicated by Link Partner.
    Bit 14 ACK 0 0 = Not acknowledged.
    Bit 15 NP 0 0 = Link Partner does not desire Next Page Transfer.
    6 6h ANER  0x0004 Bit 0 LP_AN_ABLE 0 0 = indicates that the Link Partner does not support Auto-Negotiation.
    Bit 1 PAGE_RX 0 0 = Link Code Word has not been received.
    Bit 2 NP_ABLE 1 1 = Indicates local device is able to send additional Next Pages.
    Bit 3 LP_NP_ABLE 0 0 = Link Partner does not support Next Page.
    Bit 4 PDF 0 0 = A fault has not been detected.
    Bit 5 RESERVED 0 X
    Bit 6 0
    Bit 7 0
    Bit 8 0
    Bit 9 0
    Bit 10 0
    Bit 11 0
    Bit 12 0
    Bit 13 0
    Bit 14 0
    Bit 15 0
    7 7h ANNPTR  0x2001 Bit 0 CODE 1 The default value of the CODE represents a Null Page as defined in Annex 28C of IEEE 802.3u.
    Bit 1 0
    Bit 2 0
    Bit 3 0
    Bit 4 0
    Bit 5 0
    Bit 6 0
    Bit 7 0
    Bit 8 0
    Bit 9 0
    Bit 10 0
    Bit 11 TOG_TX 0 0 = Value of toggle bit in previously transmitted Link Code Word was 1.
    Bit 12 ACK2 0 0 = Cannot comply with message.
    Bit 13 MP 1 1 = Message Page.
    Bit 14 RESERVED 0 X
    Bit 15 NP 0 0 = No other Next Page Transfer desired.
    16 10h PHYSTS  0x0605 Bit 0 LINK STATUS 1 1 = Valid link established
    Bit 1 SPEED STATUS 0 0 = 100 Mb/s mode.
    Bit 2 DUPLEX STATUS 1 1 = Full duplex mode.
    Bit 3 LOOPBACK STATUS 0 0 = Normal operation.
    Bit 4 AUTO-NEG COMPLETE 0 0 = Auto-Negotiation not complete
    Bit 5 JABBER DETECT 0 0 = No Jabber.
    Bit 6 REMOTE FAULT 0 0 = No remote fault condition detected.
    Bit 7 MII INTERRUPT 0 0 = No interrupt pending.
    Bit 8 PAGE RECEIVED 0 0 = Link Code Word Page has not been received.
    Bit 9 DESCRAMBLER LOCK 1 100Base-TX Descrambler Lock from PMD.
    Bit 10 SIGNAL DETECT 1 0 = MDI pairs normal
    Bit 11 FALSE CARRIER SENSE LATCH 0 0 = No False Carrier event has occurred.
    Bit 12 POLARITY STATUS 0 0 = Correct Polarity detected.
    Bit 13 RECEIVE ERROR LATCH 0 0 = No receive error event has occurred.
    Bit 14 MDIX MODE 0 0 = MDI pairs normal
    Bit 15 RESERVED 0 X
    17 11h MICR  0x0000 Bit 0 NT_OE 0 0 = PWRDOWN_INT is a Power Down Input.
    Bit 1 INTEN 0 0 = Disable event based interrupts.
    Bit 2 TINT 0 0 = Do not generate interrupt.
    Bit 3 RESERVED 0 X
    Bit 4 0
    Bit 5 0
    Bit 6 0
    Bit 7 0
    Bit 8 0
    Bit 9 0
    Bit 10 0
    Bit 11 0
    Bit 12 0
    Bit 13 0
    Bit 14 0
    Bit 15 0
    18 12h MISR  0x0000 Bit 0 RHF_INT_EN 0 Enable Interrupt on Receive Error Counter Register half-full event.
    Bit 1 FHF_INT_EN 0 Enable Interrupt on False Carrier Counter Register half-full event.
    Bit 2 ANC_INT_EN 0 Enable Interrupt on Auto-negotiation complete event.
    Bit 3 DUP_INT_EN 0 Enable Interrupt on change of duplex status.
    Bit 4 SPD_INT_EN 0 Enable Interrupt on change of speed status.
    Bit 5 LINK_INT_EN 0 Enable Interrupt on change of link status.
    Bit 6 ED_INT_EN 0 Enable Interrupt on energy detect event.
    Bit 7 LQ_INT_EN 0 Enable Interrupt on Link Quality Monitor event.
    Bit 8 RHF_INT 0 0 = No receive error carrier counter half-full interrupt pending.
    Bit 9 FHF_INT 0 0 = No false carrier counter half-full interrupt pending.
    Bit 10 ANC_INT 0 0 = No Auto-negotiation complete interrupt pending.
    Bit 11 DUP_INT 0 0 = No duplex status change interrupt pending.
    Bit 12 SPD_INT 0 0 = No speed status change interrupt pending.
    Bit 13 LINK_INT 0 0 = No change of link status interrupt pending.
    Bit 14 ED_INT 0 0 = No energy detect interrupt pending.
    Bit 15 LQ_INT 0 0 = No Link Quality interrupt pending.
    19 13h PAGESEL  0x0000 Bit 0 PAGE_SEL 0 0 = Extended Registers Page 0
    Bit 1 0
    Bit 2 RESERVED 0 X
    Bit 3 0
    Bit 4 0
    Bit 5 0
    Bit 6 0
    Bit 7 0
    Bit 8 0
    Bit 9 0
    Bit 10 0
    Bit 11 0
    Bit 12 0
    Bit 13 0
    Bit 14 0
    Bit 15 0
    20 14h FCSCR  0x0000 Bit 0 FCSCNT[7:0] 0 False Carrier Event Counter
    Bit 1 0
    Bit 2 0
    Bit 3 0
    Bit 4 0
    Bit 5 0
    Bit 6 0
    Bit 7 0
    Bit 8 RESERVED 0 X
    Bit 9 0
    Bit 10 0
    Bit 11 0
    Bit 12 0
    Bit 13 0
    Bit 14 0
    Bit 15 0
    21 15h RECR  0x0000 Bit 0 RXERCNT[7:0] 0 RX_ER Counter
    Bit 1 0
    Bit 2 0
    Bit 3 0
    Bit 4 0
    Bit 5 0
    Bit 6 0
    Bit 7 0
    Bit 8 RESERVED 0 X
    Bit 9 0
    Bit 10 0
    Bit 11 0
    Bit 12 0
    Bit 13 0
    Bit 14 0
    Bit 15 0
    22 16h PCSR  0x014B Bit 0 DESCRAM BYPASS 1 1 = Descrambler Bypass Enabled.
    Bit 1 SCRAM BYPASS 1 1 = Scrambler Bypass Enabled.
    Bit 2 NRZI BYPASS 0 0 = NRZI Bypass Disabled.
    Bit 3 FEFI_EN 1 1 = FEFI Mode Enabled.
    Bit 4 RESERVED 0 X
    Bit 5 FORCE 100 OK 0 0 = Normal 100 Mb/s operation.
    Bit 6 FX_EN 1 1 = Enables FX operation
    Bit 7 DESC_TIME 0 Descrambler Timeout: 0 = 722us
    Bit 8 SD_OPTION 1 1 = Default operation.
    Bit 9 SD FORCE PMA 0 0 = Normal SD operation.
    Bit 10 TQ_EN 0 0 = Normal Transmit Mode.
    Bit 11 FREE CLK 0 0 = RX_CLK phase adjusted based on alignment.
    Bit 12 RESERVED 0 X
    Bit 13 0
    Bit 14 0
    Bit 15 0
    23 17h RBR  0x0A21 Bit 0 ELAST_BUF[1:0] 1 Receive Elasticity Buffer
    Bit 1 0
    Bit 2 RX_UNF_STS 0 Normal
    Bit 3 RX_OVF_STS 0 Normal
    Bit 4 RMII_REV1_0 0 0 = CRS_DV will toggle at the end of a packet
    Bit 5 RMII_MODE 1 1 = Reduced MII Mode.
    Bit 6 SCMII_TX 0 0= Standard MII mode.
    Bit 7 SCMII_RX 0 0= Standard MII mode.
    Bit 8 PMD_LOOP 0 0= Normal Operation.
    Bit 9 TX_SOURCE 1 Full port swap (AN-1509, Para 3.3, Table 5)
    Bit 10 0
    Bit 11 RX_PORT 1
    Bit 12 0
    Bit 13 DIS_TX_OPT 0 Disable RMII TX Latency Optimization
    Bit 14 RESERVED 0 X
    Bit 15 SIM_WRITE 0 0 = Per-port write.
    24 18h LEDCR  0x0000 Bit 0 ACTLED 0 Value to force on LED_ACT/LED_COL output
    Bit 1 LNKLED 0 Value to force on LED_LINK output
    Bit 2 SPDLED 0 Value to force on LED_SPEED output
    Bit 3 DRV_ACTLED 0 0 = Normal operation
    Bit 4 DRV_LNKLED 0 0 = Normal operation
    Bit 5 DRV_SPDLED 0 0 = Normal operation
    Bit 6 BLINK_FREQ 0 0 = 6Hz
    Bit 7 0
    Bit 8 LEDACT_RX 0 0 = Activity is indicated for Transmit or Receive traffic
    Bit 9 RESERVED 0 X
    Bit 10 0
    Bit 11 0
    Bit 12 0
    Bit 13 0
    Bit 14 0
    Bit 15 0
    25 19h PHYCR  0x0021 Bit 0 PHYADDR[4:0] 1 Phy Address = 1
    Bit 1 0
    Bit 2 0
    Bit 3 0
    Bit 4 0
    Bit 5 ED_CNFG[0..1] 1 Mode 1
    Bit 6 0
    Bit 7 BP_STRETCH 0 0 = Normal operation.
    Bit 8 BIST_START 0 0 = BIST stop.
    Bit 9 BIST_STATUS 0 0 = BIST fail. Latched, cleared when BIST is stopped.
    Bit 10 PSR_15 0 0 = PSR9 selected.
    Bit 11 BIST_FE 0 0 = Normal operation.
    Bit 12 PAUSE_TX 0 Pause Transmit Negotiated
    Bit 13 PAUSE_RX 0 Pause Receive Negotiated
    Bit 14 FORCE_MDIX 0 0 = Normal operation.
    Bit 15 MDIX_EN 0 0 = Disable Auto-neg Auto-MDIX capability.
    26 1Ah 10BTSCR  0x0904 Bit 0 JABBER_DIS 0 0 = Jabber function enabled.
    Bit 1 HEARTBEAT_DIS 0 0 = Heartbeat function enabled.
    Bit 2 RESERVED 1 X
    Bit 3 RESERVED 0
    Bit 4 POLARITY 0 0 = Correct Polarity detected.
    Bit 5 RESERVED 0 X
    Bit 6 FORCE LINK 10 0 0 = Normal Link Status.
    Bit 7 LP DIS 0 0 = Transmission of NLPs is enabled.
    Bit 8 LOOPBACK 10 DIS 1 10Base-T Loopback Disable
    Bit 9 SQUELCH 0 Default Squelch ON is 330mV peak.
    Bit 10 0
    Bit 11 1
    Bit 12 RESERVED 0 X
    Bit 13 0
    Bit 14 0
    Bit 15 10BT_SERIAL 0 0 = Normal Operation.
    27 1Bh CDCTRL1  0x0000 Bit 0 CDPATTSEL[1:0] 0 00 = Data, EOP0 sequence.
    Bit 1 0
    Bit 2 2 10MEG_PATT_GAP 0 0 = 10 μs.
    Bit 3 RESERVED 0 X
    Bit 4 CDPATTEN_10 0 0 = Disabled.
    Bit 5 BIST_CONT_MODE 0 Packet BIST Continuous Mode
    Bit 6 RESERVED 0 X
    Bit 7 0
    Bit 8 BIST_ERROR_COUNT 0 BIST ERROR Counter
    Bit 9 0
    Bit 10 0
    Bit 11 0
    Bit 12 0
    Bit 13 0
    Bit 14 0
    Bit 15 0
    28 1Ch PHYCR2  0x0000 Bit 0 RESERVED 0 X
    Bit 1 0
    Bit 2 0
    Bit 3 0
    Bit 4 0
    Bit 5 0
    Bit 6 0
    Bit 7 0
    Bit 8 0
    Bit 9 SOFT_RESET 0  
    Bit 10 RESERVED 0 X
    Bit 11 0
    Bit 12 0
    Bit 13 0
    Bit 14 0
    Bit 15 0
    29 1Dh EDCR  0x6011 Bit 0 ED_DATA_COUNT 1 Energy Detect Data Threshold
    Bit 1 0
    Bit 2 0
    Bit 3 0
    Bit 4 ED_ERR_COUNT 1 Energy Detect Error Threshold
    Bit 5 0
    Bit 6 0
    Bit 7 0
    Bit 8 ED_DATA_MET 0 Energy Detect Data Threshold Met
    Bit 9 ED_ERR_MET 0 Energy Detect Error Threshold Met
    Bit 10 ED_PWR_STATE 0 Energy Detect Power State
    Bit 11 ED_BURST_DIS 0 Energy Detect Burst Disable
    Bit 12 ED_MAN 0 Energy Detect Manual Power Up/Down
    Bit 13 ED_AUTO_DOWN 1 Energy Detect Automatic Power Down
    Bit 14 ED_AUTO_UP 1 Energy Detect Automatic Power Up
    Bit 15 ED_EN 0 Energy Detect Enable

  • 0 in reply to jean-michel
    Prodigy 10 points

    Hi Vikram, Anyone,

    I am trying to make a microcontroller program a DP83849IF so that I can switch between normal mode and 'full port switch' mode.

    I have 'normal mode' working. But, cannot get the 'full port switch' mode to work.

    The DP83849IF is connected to the micro-controller MAC via RMII port A.

    In 'normal mode' I have bits 9,10,11 and 12 of the RBR register set as 0000 for both register sets and I see data on RMII A RXD0 (Pin 4)and RXD1 (Pin 5). And comms works!

    In 'full port switch' mode I have bits 9,10,11 and 12 of the RBR register set as 0101 for both register sets. This is the suggested configuration for Full Port Swap. However,  I see nothing on RMII A RXD0 (Pin 4)and RXD1 (Pin 5).

    Does anyone have any suggestions?

    Thanks in advance,

    Jean-Michel.

  • 0 in reply to jean-michel
    TI__Genius 16030 points

    Hello Jean,

    Is the configuration still the same as you shared earlier in the block diagram? With full port switch, you are supposed see data on port A coming from channel B. Can you check the link-status of channel B (as I described in the attachment earlier)?

    --

    Regards,

    Vikram