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DP83867ERGZ-R-EVM: recommended wire

Part Number: DP83867ERGZ-R-EVM
Other Parts Discussed in Thread: TEST, TIDA-00928

Hi team,

Regarding DP83867ERGZ-R-EVM, the customer has the following questions:

The pins on the board, such as TX_ D0~4, RX_ D0~4, RX_ CLK, TX_ CLK, What kind of wire is used to connect with MAC or FPGA? If the Dupont Line is inserted into the pin, will there be signal quality or data synchronization problems? What kind of connector should be used? What are the requirements of connector? Is there a recommended purchase link

Best Regards,

Amy

  • Hello Amy,

    Thank you for the query.

    These signals  signal carries data to/from the PHY to the MAC in RGMII mode.

    These signals have routing constraints that are critical for communication

    See below a summary from the data sheet 

    9.2.2.1.2 RGMII Layout Guidelines

    • RGMII signals are single-ended signals.

    • Traces must be routed with impedance of 50 Ω to ground.

    • Skew between TXD[3:0] lines should be less than 11 ps, which correlates to 60 mil for standard FR4.

    • Skew between RXD[3:0] lines should be less than 11 ps, which correlates to 60 mil for standard FR4.

    • Keep trace lengths as short as possible; less than 2 inches is recommended with less than 6 inches as maximum length.

    • Configurable clock skew for GTX_CLK and RX_CLK. – Clock skew for RX and TX paths can be optimized independently. – Clock skew is adjustable in 0.25-ns increments (through register).

    If the hot does not have a mating connector to the EVM, you may have to make a interposer board to be able to test the communication.

    I do not have a part number for the connectors. Check out samtec connectors.

    We did similar interface for 10/100 in TIDA-00928. You could use that as a reference.

    Regards,

    Sreenivasa