Hello Team,
My Customer is using the SN65MLVD206 for a SPI clock transmission/reception. RE & DE pins are wire-ored (shorted together) and connected to a GPIO of a uC. The uC controls the state of these pins by pulling high or low. Will there be an issue using this scheme? uC in this case can be SPI master or slave hence the need for bidirectional clock signal.
Similar to the above case, pins R & D are wire-ored of the same device for the same reason. is OK to use it this way?
Regards,
Renan