When PRBS31 10.3125 Gpps signal is input and the register is controlled as follows, CDR is unlock.
Could you tell me the correct sequence?
Without CDR reset(0x0A,0x00,0x0C) & assert 0x0A,0x0C,0x0C)command,CDR will be lock.
(ADDR, VALUE, MASK)
(0xFF,0x0C,0x0C)
(0x00,0x04,0x04)
(0x0A,0x0C,0x0C)
(0x31,0x00,0x60)
(0x03,0x00,0xFF)
(0x40,0x00,0xFF)
(0x1E,0x08,0x08)
(0x2D,0x08,0x08)
(0x2D,0x02,0x07)
(0x15,0x00,0x47)
(0x0A,0x00,0x0C)