This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

XIO3130: XIO3130 Questions

Part Number: XIO3130

HI there,

I have some questions on the XIO3130 :

Here they are:

  1. Serial configuration usage
    As I understand the datasheet, if the device detects the presence of a configuration eeprom, it *expects* the contents to be completely programmed – is this correct? In other words, leaving the device unprogrammed (default state = 0xFFs) is not an option if the pull-up is present on the external SCL pin.

    1b) My second question with regards to this is that in order to permit the disabling of the external serial eeprom, the device should be able to boot by default into a minimally functional mode (perhaps not optimal, but at least as far as the upstream port is concerned, functional). Is this a reasonable interpretation?
  2. Absence of AC terminations on reference clock signals.
    On your evaluation board, there are no AC termination caps on the reference clock signals to the downstream ports… There is nothing in the datasheet about this requirement either. Since our downstream devices are on the board itself (no external slots are provided), do we simply not need them? Other similar devices suggest the use of AC decoupling caps on the clock reference lines…
  3. REFR0/REFR1 connectivity
    The datasheet indicates that a resistor should be connected between these terminals but does not specify a value. The EVM indicates there 2 resistors, one of 14.4KOhm and a second of 232 Ohm… Can you provide further clarification as to the precise value needed, and why 2 resistors were used? (Was it related to the overall value not being available in a single resistor?)
  4. GRSTn vs UP_PERSTn
    These 2 terminals seem to do essentially the same thing. Rather than supply the same reset signal to both terminals, we would prefer to only use one of them. Can we use UP_RESETn and ensure there is a pull-up resistor on GRSTn?
  5. Disabling a downstream port
    Is there a preferred method to completely disable a downstream port (we only need 2 of the three available)? It’s unclear from the datasheet if we need to terminate the interface signals in a particular way, or if we need to use pull-ups on DNx_DPSTRP (‘3’, in our case) and GPIO8 (PRESENTn) and leave everything else unconnected. Obviously, the eval board does not really clarify this use-case.

Thanks for your help and support!

  • Hi Mark,

    Please note comments:

    1a). Correct EEPROM should be programmed once there is pull-up on SCL.

    1b). On rising edge of PERSTbar and seeing pull up on SCL, device loads configurations from EEPROM. The user can disable EEPROM control afterward. In a case, The point is that after every PERSTbar device samples SCL to check if it can access EEPROM.

    2). In PCIe applications we typically see DC coupling of the 100MHz reference clock. Therefor we don't need AC coupling Caps on ref. clock.

    3). This sets the reference current and thus it is very important to use as close value as possible. This is why we are using 1% tolerance and two Resistors.

    4). Sure you can use UP_PERST# assuming upstream or master device is driving this signal.

    5). DNx_DPSTRP allows GPIOs to be used as power good signals and downstream port present signal.To disable downstream port, we need to pull PRESENTn GPIO high.