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Texas Instruments (TI) Interface support forum is an extensive online knowledge base where millions of technical questions and solutions are available 24/7. You can search interface IC content or ask technical support questions on everything from ESD protection to interfacing with USB, Ethernet, and HDMI. Find the right solution for your circuit design challenges by using our TI E2E™ support forums that are supported by thousands of contributing TI experts.
Frequent questions
  • [FAQ] DP83TD510E: Can we use a transformer instead of Capacitor for AC coupling on the MDI side for DP83TD510?

    Hillman Lin
    Hillman Lin
    Part Number: DP83TD510E Yes, transformer can be used for filtering out the DC signal when the data is passing through the MDI side. In fact, we use transformer to filter out the AC signal in the Power over Data Line (PoDL) application. Here are the…
    • over 3 years ago
    • Interface
    • Interface forum
  • [FAQ] What is the difference between RMII slave signaling and RMII master signaling?

    Hillman Lin
    Hillman Lin
    RMII slave signaling is connecting 50MHz Crystal to two XI pin of the PHY and/or MAC RMII master signaling is connection 25MHz Crystal to one Master and provide a 50MHz reference lock through REF_CLK pin to the XI pin of the slave side. Slave side does…
    • over 3 years ago
    • Interface
    • Interface forum
  • [FAQ] DP83TC812R-Q1: How can I connect PHYs back to back over RMII?

    Hillman Lin
    Hillman Lin
    Part Number: DP83TC812R-Q1 There are two type of mode that RMII can support: RMII normal mode and RMII Repeater mode: RMII normal mode is also known as MAC to PHY RMII connection. This mode is set as default mode in DP83TC812 so it did not need…
    • over 3 years ago
    • Interface
    • Interface forum
  • [FAQ] DP83TC811S-Q1: Why is Slave/Managed mode PHY linking up with Master/Autonomous PHY link partner?

    Gerome Cacho
    Gerome Cacho
    Part Number: DP83TC811S-Q1 Other Parts Discussed in Thread: DP83TC811R-Q1 When using DP83TC811S-Q1 (or DP83TC811R-Q1), and setting the PHY into managed mode as a slave device via bootstrapping settings, if this device is connected to a master link partner…
    • over 4 years ago
    • Interface
    • Interface forum
  • [FAQ] DS90UH949-Q1: Disable HDCP to work with UB Deserializer

    Alex Reid1
    Alex Reid1
    Part Number: DS90UH949-Q1 Hello, My customer would like to use DS90 UH949 -Q1 devices in place of the DS90 UB949A -Q1 to keep production running. In reviewing the details they have the following questions. Can the HDCP function be disabled? If…
    • Answered
    • over 4 years ago
    • Interface
    • Interface forum
  • [FAQ] Why am I getting "clause-45 not supported" and "error-95" errors with PHY drivers?

    Vikram Sharma
    Vikram Sharma
    Possible reason can be : - "phy_read_mmd" and "phy_write_mmd" are not supported in your kernel version (if version is old). Possible solution to be evaluated : - Change "phy_write_mmd" to "phy_write_mmd_indirect" function and do the corresponding…
    • over 4 years ago
    • Interface
    • Interface forum
  • [FAQ] DS90UB960-Q1: BIST Duration

    ReedKacz
    ReedKacz
    Part Number: DS90UB960-Q1 Hi Team, What is the recommended duration to run the BIST? Thanks Reed
    • Answered
    • over 4 years ago
    • Interface
    • Interface forum
  • [FAQ] How to select correct RGMII delay mode for PHY and MAC?

    Vikram Sharma
    Vikram Sharma
    RGMII standard asks for the introduction of delay in the clock (RX_CLK/TX_CLK) with respect to the respective data (RX_D*/RX_CTRL or TX_D*/TX_CTRL). This delay can be introduced at the source of the clock or at the receiver side. Following table should…
    • over 4 years ago
    • Interface
    • Interface forum
  • [FAQ] How to select the crystal's ppm specification for an Ethernet system?

    Vikram Sharma
    Vikram Sharma
    Other Parts Discussed in Thread: DP83TC811 Ethernet data travels effectively from one MAC to another MAC with two Ethernet PHYs in between. Each of these 4 ICs can have their own reference clocks and crystal attached to each is the usual source of this…
    • over 4 years ago
    • Interface
    • Interface forum
  • [FAQ] DP83867IR: DP83867 digital loopback fail, how to set MII and PCS loopback

    Richard Yang1
    Richard Yang1
    Part Number: DP83867IR Hi Team: Customer side need our help to find the root cause of DP83867 Communication failure issue from one failed board . could you please help to take a look at the attached , customer need to know How to enable MII and PCS…
    • over 4 years ago
    • Interface
    • Interface forum
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  • Answered

    TRS3223-Q1: Schematic Review Request 0 Locked

    402 views
    2 replies
    Latest over 1 year ago
    by Kenneth Lee
  • Answered

    DP83TD510E-EVM: AN (MMD7) registers return zero value 0 Locked

    620 views
    4 replies
    Latest over 1 year ago
    by Eelco Simonse
  • Answered

    DP83TC812R-Q1: In sleep mode, is it required to turn off all power supplies to DP83TC812R-Q1 except VSLEEP pin? 0 Locked

    458 views
    4 replies
    Latest over 1 year ago
    by Melissa Chang
  • Not Answered

    DS90UB948-Q1: DS90UB948 entering the Linux kernel to work after bootloader, the first byte read is correct, and the second byte read fails and reset. 0 Locked

    300 views
    1 reply
    Latest over 1 year ago
    by Fadi Abdulhameed
  • Suggested Answer

    PCA9546A: Clarification on MUX 0 Locked

    327 views
    1 reply
    Latest over 1 year ago
    by Clemens Ladisch
  • Not Answered

    TCAN1043A-Q1: TCAN1043 IC Operation 0 Locked

    340 views
    1 reply
    Latest over 1 year ago
    by Sean Guo
  • Answered

    SN65DSI86: Tvcc_ramp is about 0.1ms, any risks 0 Locked

    272 views
    1 reply
    Latest over 1 year ago
    by Vishesh Pithadiya
  • Answered

    DP83867IR: What is the min max values Internal pullup and pulldown resistors 0 Locked

    456 views
    6 replies
    Latest over 1 year ago
    by William Weishaupt
  • Answered

    LMH0341: Yes 0 Locked

    296 views
    1 reply
    Latest over 1 year ago
    by Nasser Mohammadi
  • Suggested Answer

    TFP410: TFP410 - Internally deterministic? Use two in pararlel for dual-link DVI? 0 Locked

    512 views
    3 replies
    Latest over 1 year ago
    by David (ASIC) Liu
  • Suggested Answer

    LMH0070: LMH0070SQE/NOPB 0 Locked

    291 views
    1 reply
    Latest over 1 year ago
    by Nasser Mohammadi
  • Answered

    DS90UB954-Q1: How to configure for Eye pattern test using CMLOUT? 0 Locked

    803 views
    5 replies
    Latest over 1 year ago
    by Hamzeh Jaradat
  • Answered

    DP83TG720R-Q1: DP83TG720RWRHATQ1 0 Locked

    407 views
    4 replies
    Latest over 1 year ago
    by Mehdi Noroozi
  • Suggested Answer

    SN75LVPE5421: how can I get a sigcon RTE and profile that can support SN75LVPE5421 and SN75LVPE5412 0 Locked

    457 views
    3 replies
    Latest over 1 year ago
    by Nasser Mohammadi
  • Suggested Answer

    TCAN4550: Alternative power scheme options 0 Locked

    381 views
    1 reply
    Latest over 1 year ago
    by Jonathan Nerger
  • Not Answered

    TMUXHS4212: recommended AC coupling cap placement for 10G SFI application 0 Locked

    446 views
    1 reply
    Latest over 1 year ago
    by Brian Zhou
  • Suggested Answer

    TCAN4551-Q1: TCAN4551 0 Locked

    488 views
    1 reply
    Latest over 1 year ago
    by Jonathan Nerger
  • Suggested Answer

    TCAN4550: TCAN4550 0 Locked

    349 views
    1 reply
    Latest over 1 year ago
    by Jonathan Nerger
  • Answered

    ESDS311: ESD protection for microphone inputs on the TLV320AIC3106 codec 0 Locked

    841 views
    3 replies
    Latest over 1 year ago
    by Sebastian Muriel
  • Suggested Answer

    TCA9548A-Q1: Does the number of enabled gates affect the SCL rise time? 0 Locked

    587 views
    7 replies
    Latest over 1 year ago
    by Clemens Ladisch
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