Interface forum - Recent Threads

TCAN2845-Q1: The dynamic ripple test of TCAN28453 exceeded 2%.

xiaolin Han — Mon, 29 Jun 2026 03:47:06 GMT

Part Number: TCAN2845-Q1

Connect the VEXCC and VCC1 pins of TCAN28453 together for use, and test the dynamic load ripple exceeding the 2% range.

The test conditions are as follows: test frequency 100Hz, load current 0 - 174mA, duty cycle 50%, current change rate 3A/uS

TRS232E: Can TRS232EIDWR directly replace MAX232ECDWR while keeping all capacitors at 10 µF?

Takuya Noguchi — Mon, 29 Jun 2026 00:25:14 GMT

Part Number: TRS232E
Other Parts Discussed in Thread: MAX232E

We are considering replacing the MAX232ECDWR with the TRS232EIDWR because the MAX232ECDWR has reached end of life (EOL).

In our current design, we use 10-µF capacitors for C1 through C4 and the VCC bypass capacitor (Cbypass), based on the following statements in the MAX232E datasheet:

"The MAX232E requires 1µF capacitors, although capacitors up to 10µF can be used without harm."
"Bypass VCC to ground with at least 1µF."

In the TRS232EIDWR datasheet, the recommended application circuit shows the capacitors, but we could not find any information regarding the allowable capacitor value range or the maximum recommended capacitance.

Can we replace the MAX232ECDWR with the TRS232EIDWR without changing the surrounding component values, specifically keeping C1 through C4 and Cbypass at 10µF?

If using 10-µF capacitors is not recommended, could you please advise the recommended capacitor values and any design considerations for the TRS232EIDWR?

Thank you for your support.

TDP142-Q1: Schematic and application review

Che Wen Yeh — Mon, 29 Jun 2026 00:10:22 GMT

Part Number: TDP142-Q1

Hi Teams,

We are using the TDP142RGFRQ1 in our design. Please refer to the attached schematic and help review whether the connection architecture is correct.

Is this configuration considered a Source Application?

Also, could you please explain why the I2C lines are connected to the AUX channel?

In addition, could you clarify whether the Sink Application refers to a configuration where the signal enters from the left connector and exits from the right connector, similar to a dongle or adapter application?

Thanks.

TDP142RGFRQ1_20260624.pptx

TMUXHS221: TMUXHS221 MUX for UART

Pream krishna illa — Sun, 28 Jun 2026 12:08:06 GMT

Part Number: TMUXHS221

Hi Team,

We are planing to use TMUXHS221NKGT part in our design for switching between two UART interfaces (refer to the image)

could you confirm whether TMUXHS221 can used for UART application as the datasheet is mostly focused on USB2.0

TCA9511A: Customer claims TCA9511ADGKR parts from Mouser (distributor) are 'bad' -- scramble I2C comm lines in the circuit

Daniel Rapp — Fri, 26 Jun 2026 22:49:16 GMT

Part Number: TCA9511A

To TI Support Team

We have a customer who purchased and received 120pcs of TI I2C buffer chip part TCA9511ADGKR on 5/5/2026 (Inv# 90198318 on Mouser PO# 029-YD677, Lot code 0023348ASH and Date code 2015 in YYWW). They state that there is an issue of the parts scrambling their I2C communication lines. They know it is the part causing the issue as they removed the chip and replaced it with the same part number from another board from their internal stock, and then it worked fine. The customer thinks the lot at Mouser may be bad. Please review the customer's below comments regarding this. We need to know if there is something the customer can check that may resolve this or if this needs to go to Failure Analysis for Quality to review (?).

Can you help us with this?

[customer comments]
--------------------------------------------
"We have discovered an issue with the buffer located at U24 on the HUSKY UI Board (B139591) that was shipped to fulfil PO 26310. The part number the buffer is TCA9511ADGKR.

We are seeing that instead of cleaning the I2C lines, it is scrambling them, causing the board not to function correctly. Our electrical engineering team then swapped the component at U24 with internal stock of the same component, and the swap immediately fixed the issue. We noticed some appearance discrepancies of our stock of TCA9511ADGKR vs. the TCA9511ADGKR that came on the boards from Summit and suspect an issue with your stock of these chips."

Thanks,
(Service Order# 558311)
Dan Rapp, Technical Support Representative II
Mouser Electronics, Inc.
817-804-3800 x2755 Direct | www.mouser.com
The Newest Products for Your Newest Designs®

TUSB8044A: TUSB804xx Host Controlled Per Port Power Reset

Brett Padfield — Fri, 26 Jun 2026 15:27:25 GMT

Part Number: TUSB8044A
Other Parts Discussed in Thread: TUSB8042A

Hi, I'm currently designing a USB 3.0 hub that requires host-commanded per-port power cycling. I've been reviewing the TUSB8042A datasheet but I'm having trouble finding a clear answer on a few things:

Is there a native mechanism to toggle per-port VBUS from an upstream host command, either through the port control pins or overcurrent pins? Is external hardware beyond a standard power switch IC required to achieve this? Does TI offer any hub IC that supports this natively without an external MCU?

I want to make sure I'm not missing an obvious use case or recommended reference design before committing to an architecture. Any guidance or application note references would be appreciated. Thank you.

DP83822IF: DP83822IF media converter far end fault propagation

Jean-Francois Bilodeau — Fri, 26 Jun 2026 14:55:44 GMT

Part Number: DP83822IF
Other Parts Discussed in Thread: DP83843

Hello TI customer support.

We have successfully implemented in Q4 2024 a media converter application using 2x DP83822IF PHY in RMII back to back mode. Hundreds of units have shipped with no issues reported.

Recently a customer came back with a very targeted issue when our design is connected to a legacy piece of equipment based on TI DP83843PHY.

Both units communicate just fine after a power-on reset.

I have nailed down the problem to what I think is a Far End Fault not propogating between both equipments under specific circumstances.

Equipment #1 : Our device with DP83822IF media converter (Intel MAC <-> 100Base-TX <-> DP83822IF configured as CU PHY <-> RMII 50MHz <-> DP83822IF configured as FX PHY <-> 100Base-FX)

Equipment #2 : Customer legacy device with DP83843 PHY

If I disconnect the TX fiber on Equipment #2 OR RX fiber on Equipment #1 (same fiber..), the communication is momentarily lost, but will automatically come back.

Equipment #1 and Equipment #2 shows link down status then link up when I reconnect this fiber. This seems to indicate that DP83822IF on Equipment #1 is sending the Far End Fault to Equipment #2

Now, If I disconnect the RX fiber on equipment #2 OR TX fiber on Equipment #1, the communication is lost and never comes back.

It seems like either Equipment #2 (DP83843) does NOT send a Far End Fault signal, or Equipment #1 (DP83822IF) does NOT receive or correctly identify an incoming Far End Fault signal.

Equipment #1 shows link-up is still valid, and Equipment #2 shows link-up is still valid, even though the incoming fiber signal to Equipment #2 has been lost due to unconnected fiber.

Do you have an idea of what may be happening here?

TCAN3413: TCAN3413 does not have an CANH CANL input model in the IBIS file.

Joseph Dvorsky — Fri, 26 Jun 2026 14:54:21 GMT

Part Number: TCAN3413

TI recommended to use the tcan33x.ibs file since the tcan34xx.ibs file fails parser checks. I downloaded tcan33xx.ibs. It does not have a differential input model to be used in simulation.

ESD204: About TI-JESD204-IP

Quside Technologies SL — Fri, 26 Jun 2026 14:29:38 GMT

Part Number: ESD204

Hello, I would like to know if the TI-JESD204-IP, which I just downloaded from your website, is a fully functional IP for testing purposes or if there are any restrictions on its use for testing.
We recently purchased the corresponding EvalKit from your website. My company is Quside Technologies.

Thank you.

TUSB211A-Q1: Ferrite Bead

Edgardo Torres — Fri, 26 Jun 2026 14:03:24 GMT

Part Number: TUSB211A-Q1

One more follow-up regarding the TUSB211A-Q1 reference schematic

The datasheet specifies a ferrite bead of 100ohm @ 100MHz on the VCC supply. We are unable to source an exact 100ohm @ 100MHz part

Is 120ohm @ 100MHz acceptable as a substitute on the TUSB211A-Q1 VCC, or is the 100ohm value critical for proper device operation? If a specific tolerance range is acceptable (e.g., 80–120ohm), please advise.

Thank you.

Best regards,
E. Torres

SN65DPHY440SS: SN65DPHY440SSRHRT IBIS MODEL

Harrick Wang — Fri, 26 Jun 2026 13:12:22 GMT

Part Number: SN65DPHY440SS

Could we provide IBIS model of SN65DPHY440SSRHRT

DP83TC811S-Q1: Interfacing DP83TC811S-Q1 to ZYNQMP GEM using SGMII

Gary Halfyard — Fri, 26 Jun 2026 12:09:13 GMT

Part Number: DP83TC811S-Q1

Are there any examples reference designs or guides that provide a worked example of how to get the DP83TC811S-Q1 100base-T1 PHY to work with a ZYNQMP (ZU3EG) GEM over SGMII ? I am using petalinux and have tried everything.

I believe the PHY strap configuration is correct and I can see from the LEDs that the link status is good and activity is detected on the line. The PHY driver successfully probes and I can manually read the internal registers but I cannot get the MAC and the PHY to communicate.

I have verified all the basics, physical connections are no swapped nor polarity reversed. The PSGTR has a 125MHz reference clock and the device tree correctly maps SGMII->PSGTR1->GEM1.

I understand that the SGMII Line rate needs to stay at 1.25Gbps and the 100Mbps line rate must use rate adaption. The GEM side seems to need to complete AN for the PCS to get enabled but that does not work unless it is advertised at 1000baseT which then does not enable rate adaption, and on it goes.

Has anybody tried this architecture and managed to get it working or is it a dead-end ?

DP83867E: RGMII interface Eye mask Constraints

Mythili Balakrishnan — Fri, 26 Jun 2026 12:06:06 GMT

Part Number: DP83867E

Hi Team,

We are using DP83867E part in our custom design for RGMII interface. We are supposed to do Signal integrity simulation for these signals. Could you please share the eye mask constraints for the RGMII TX and RX signals if it is available.

Warm Regards,

Mythili B

SN65MLVD080: SN65MLVD080: Can D (Driver Input) and R (Receiver Output) be connected to a single FPGA bidirectional I/O?

Rohith M — Fri, 26 Jun 2026 11:47:18 GMT

Part Number: SN65MLVD080

Hi TI Team,

I am using the SN65MLVD080 in a half-duplex M-LVDS application with an FPGA.

To reduce FPGA I/O count, I am evaluating whether the Driver Input (D) and Receiver Output (R) pins of each channel can be connected together and interfaced to a single FPGA bidirectional (tri-state) I/O.

I would like to understand whether directly connecting D and R together is a supported or recommended implementation.

My questions are:

1. Can D and R be directly shorted together and connected to a single FPGA bidirectional I/O?
2. If not, what prevents this approach? Is it due to output contention, internal device architecture, or another limitation?
3. Is there a TI-recommended circuit to achieve a single FPGA data I/O per channel using this transceiver?
4. If direct connection is not recommended, would adding external components (such as a resistor or logic gate) make this implementation acceptable?

Thank you.

DP83TG721S-Q1: Feritte Beads definition

Katharina Ehmke — Fri, 26 Jun 2026 08:42:40 GMT

Part Number: DP83TG721S-Q1

Hi team,

may I ask for answer in regards to pending questions:

1) Why is 100MHz the decisive frequency for the Ethernet transceiver DP83TG721S Q1? It is the 4th overtone of the quartz frequency. Why is the fundamental frequency of 25MHz not decisive in that case? Why are there two different ferrite beads chosen? The given answer does not explain all these questions
2) Does it mean in case EMC performance can be ensured without ferrite beads that TI does not see a necessity to implement the ferrite beads?

Appreciate it!

Katharina

DS90UB971-Q1: X-Ray Limitation

Evan Wang — Fri, 26 Jun 2026 08:28:35 GMT

Part Number: DS90UB971-Q1

Hi team,

Customer would like to know whether our 971 has any X-ray related limitation, including X-ray intensity, explosure time...etc?

Thank you.

------------------------------------------------------------------------------------------------

The supplier shall ensure that all semi-conductors and all other components, including flash memory and NAND flash, are not exposed to X-ray radiation beyond the limits specified by the component manufacturer.

This includes defining the number of times a device can pass through the X-ray machine and the cumulative radiation energy (measured in Rads) does not exceed the component manufacturers specified tolerances.

The supplier shall verify the maximum allowable radiation exposure (both intensity and duration) for each type of device with the component manufacturer.

DS320PR410: Request for DS320PR410 EEPROM Programming Documentation (Equivalent to DS160PR410 Guide)

Li Hongyan — Fri, 26 Jun 2026 08:26:59 GMT

Part Number: DS320PR410
Other Parts Discussed in Thread: DS160PR410

Dear TI Support Team,

I am currently working on the system integration and EEPROM-based configuration of the DS320PR410 PCIe Gen5 redriver for an internal hardware development project.

While reviewing the available documentation, I found that the DS320PR410 Programmer’s Guide (SNLU335) does not include the detailed EEPROM bit mapping or hex generation guidance that is provided for the DS160PR410 (e.g., SMBus-to-EEPROM bit mapping tables, recommended EEPROM data per CTLE setting, header definition, common-channel mode, etc.).

The DS160PR410 documentation has been extremely helpful for understanding:

EEPROM base header structure
Common channel vs per-channel data layout
SMBus register-to-EEPROM bit mapping
Recommended EEPROM data values per CTLE index

For DS320PR410, I would like to request equivalent material, specifically:

EEPROM bit mapping table (SMBus register ↔ EEPROM address/bit)
EEPROM header / layout definition (including common channel behavior, multi-device address mapping, CRC, etc.)
Recommended EEPROM data values per CTLE / EQ setting
Any application note related to DS320PR410 EEPROM programming

In addition, I attempted to download the latest DS320PR410 GUI (v3.2) referenced in the programmer’s guide, but only v3.0 is available on TI.com. Could you please provide:

Access to the latest GUI version (v3.2 or above)
Any utility that can generate EEPROM hex from register configuration

Your support is greatly appreciated, and I look forward to your response.

PCA9518: 2ch I2C hub needed

Luke Sakamoto — Fri, 26 Jun 2026 07:56:03 GMT

Part Number: PCA9518

Hi INT team,

My customer is looking for an I2C buffer(repeater) but with multiple outputs.

3-channel (in total) I2C bus repeater/buffer (4-channel acceptable)
All channels must be active simultaneously (true bus repeater, NOT a multiplexer)
Dual power supply configuration:
- Supply A → 2 I2C channels
- Supply B → 1 I2C channel

Can you reccomend me one a solution to achieve this?

thanks,

Luke

DP83826AE: DP83826AERHBR Schematic Review

Min Hisen Kao — Fri, 26 Jun 2026 06:52:24 GMT

Part Number: DP83826AE

Hi Support Team,

Could you please help review the schematic design for the DP83826AERHBR? If the resolution is not clear enough, please provide your email address, and I can forward the original file to you.

TUSB8020B: How to enter low power mode

Eileen Hu — Fri, 26 Jun 2026 03:48:19 GMT

Part Number: TUSB8020B

Hi team,

For TUSB8020B, how to enter the power mode? How to configure?

Regards,

Eileen

DS90UR910-Q1: No signal output when paired with UB927

Wei Xiao — Thu, 25 Jun 2026 22:39:25 GMT

Part Number: DS90UR910-Q1

We have a proven working well (with UR905) board with UR910 on it. However, when we use it to pair with UB927 which was put in backward compatibility mode, we cannot get any MIPI output from UR910(measured with a good Oscilloscope), while the LOCK and PASS pins both are stably high. The board with UB927 is also proven good, for, if we use board with UR906, the output is normal. Would someone please shed some light on how to fix the issue? Much appreciated.

TUSB1210EVM: TUSB1210EVM, Using SN74AVC16T245 Level Shifter for 3.3V to 1.8V for VDDIO on ULPI

Kaushik Velidandla — Thu, 25 Jun 2026 19:49:27 GMT

Part Number: TUSB1210EVM
Other Parts Discussed in Thread: SN74AVC16T245, SN74AXC8T245, TUSB1210, SN74AXC4T245, SN74AVC4T245

Hello all,

I am designing a setup for a functional evaluation of a TUSB1210EVM, interfacing with OpenH743I-C Standard, STM32H7 Development Board.

Issue I am running into is the operation of the VDDIO ULPI interface of the TUSB1210 functioning at a voltage level of 1.8V, while the ULPI VDDIO rail of the STM32 Dev Board operates at 3.3V Logic Level. I would like to know if it is viable to use multiple voltage translators, such as the SN74AVC16T245, to bridge the disparity in voltages. I have seen discussions on this forum before in regards to the option being a possible solution, but would just like to confirm a plan. I have also been considering the SN74AXC8T245 and the SN74AXC4T245

I know however, that there are issues that arise with delay time, so I would like to ask for any advice at how to solve this issue.

Thank you!

DP83869HM: Ping test blink led but fail.

Nicolas Bouquet — Thu, 25 Jun 2026 16:56:12 GMT

Part Number: DP83869HM
Other Parts Discussed in Thread: DP83869, DP83869EVM

Hello,

I have a STM32MP257 <> DP83869HM <> SFP 100Mbps <> OS1 fiber <> TPlink MC100CM converter <> ETH <> linux PC

DP83869 power rails are clean, bias is 1V and clean. CLKo is 25MHz and clean.

From the STM32 point of view, the IF is UP. I'm using 4 status led : Link up, Tx, Rx, TXRX fail

When the STM32 pings the computer, DP83869 Tx led blink, TPlink converter blink
When the computer pings the STM32, DP83869 Rx led blink, TPlink converter blink

But all ping fails.

Below is what I see with a scope

SFP.LOS = 0 => OK
SFP.TxDIS = 0 => OK
SFP.TxFault = 0 => OK
SFP.DET = 0 => OK
SFP.RS =1 => OK

FX.nRST OK
FX.CLKo 25MHz
FX.TXCLK 2.5MHz (25MHz when link is up)
FX.RXCLK 2.5MHz (25MHz when link is up)
FX.nINT 0 =>>> is it normal that the nIRQ is stalled at 0 ?

Link LED ON
Tx/Rx Error LED OFF
Tx/Rx Active LED blink when pinging

MDIO reg reading:
0x11 = 0x0402
0x1DF = 0x0002
0xC00 = 0x2100
0xC01 = 0x614D

Following the troubleshootong guide, I tried a BIST test with a fiber looping the Tx/Rx slot of the SFP module. This test fails:

write Reg 0x0016 = 0xF000
read Reg 0x17 = 0x40, bit 11 is not set.

Sometimes, FX_INT_STS (0xC19 reg) is showing a FEF error (value 0x0210)

At this point, I really do not see what other test to do. Any help appreciated.

Thanks

(below is the device tree config, if it can help)

&eth2 {
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&eth2_rgmii_pins_b>;
	pinctrl-1 = <&eth2_rgmii_sleep_pins_b>;
	phy-mode = "rgmii-txid";
	max-speed = <100>;
	phy-handle = <&eth2_phy>;
	st,ext-phyclk;
	status = "okay";

	sfp0: sfp {
		compatible = "sff,sfp";
		i2c-bus = <&i2c6>;
		mod-def0-gpios = <&gpioh 10 GPIO_ACTIVE_LOW>;
		los-gpios = <&gpioe 1 GPIO_ACTIVE_LOW>;
		tx-fault-gpios = <&gpioe 3 GPIO_ACTIVE_LOW>;
		tx-disable-gpios = <&gpioe 2 GPIO_ACTIVE_LOW>;
		rate-select0-gpios = <&gpioe 5 GPIO_ACTIVE_LOW>;
	};

	mdio {
		compatible = "snps,dwmac-mdio";
		#address-cells = <1>;
		#size-cells = <0>;

		eth2_phy: ethernet-phy@0 {
			/* compatible = "ethernet-phy-id2000.a0f3"; */
			reg = <0>;

			clocks = <&rcc CK_KER_ETH2>;
			interrupt-parent = <&gpiog>;
			interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
			reset-gpios = <&gpiob 2 GPIO_ACTIVE_HIGH>;
			reset-assert-us = <50000>;
			reset-deassert-us = <500000>;
			ti,op-mode = <DP83869_RGMII_100_BASE>;
			max-speed = <100>;
			sfp = <&sfp0>;
			modif,quirk-disable-clk-125;
                        modif,quirk-leds-cfg1 = <0xd230>;
                        modif,quirk-gpio-mux-ctrl = <0x00ba>;
		};
    	};
};

DS90UB954-Q1: Register configuration suggestion

Hanbing Xiao — Thu, 25 Jun 2026 16:53:07 GMT

Part Number: DS90UB954-Q1

Hi team

Customer is going to use our 953/954 in their camera module. But they need to configure the register based on below requirement.

The CSI_CLK output from the 954 is dual-clock on the hardware side. However, since the customer's previous camera configurations all used single-clock, please configure the CSI_CLK as single-clock. The host side provides an external sync signal to GPIO_0 (Pin 17, FSIN) of the 953, a reset signal to GPIO_1 (Pin 18, RST), and a write protection signal for FLASH to GPIO_2 (Pin 27, WP). The reset signal pulse width is 50 µs, and the external sync signal frequency is 30 Hz.

Can you please share the recommended register configuation file?

Hanbing

BQ79600EVM: Your request for access to BQ79600-Q1-EVALUATION has been denied

Minhyeok Park — Thu, 25 Jun 2026 15:40:19 GMT

Part Number: BQ79600EVM
Other Parts Discussed in Thread: LP-AM263,

I purchased TI's BQ79600EVM, BQ79616EVM, and LP-AM263, but I am unable to share the related update source code.

Can i get those file?

name : Minhyeok Park

company : choongnam university

email address : 202551068@o.cnu.ac.kr

country : Daejeon, South Korea

BQ79600-FMEDA

BQ79600-Q1-FUNCTIONAL-SAFETY-DOCS

BQ79600-Q1-DEVELOPMENT

BQ79600-Q1-EVALUATION

BQ7X61X-Q1-EVALUATION

BQ7X61X-Q1-DEVELOPMENT

BQ7X61X-Q1-FMEDA