Interface forum - Recent Threads

TPD1E1B04: different body mark

Hong Jun — Mon, 11 May 2026 02:17:46 GMT

Part Number: TPD1E1B04

For GEC1H-5864558, the component marking does not match the drawing.
Could you please help check to confirm whether this is the correct part?

MPN: TPD1E1B04DPYR
Body marking: A5

TUSB8020B: USB is not attached

Andrea Hwang — Mon, 11 May 2026 01:34:31 GMT

Part Number: TUSB8020B

The first batch of PCBs has arrived; however, we are experiencing issues with the USB functionality.
After reviewing the schematics, I have identified two primary errors

1. Power Switch Port Swap
- The input and output ports of the USB power switch were inadvertently swapped.
2. Power-on Timing Mismatch
- The timing sequence between VDD and the Global Reset (GRST) does not align with the datasheet specifications.

I am currently testing a hardware fix by increasing the capacitance on the GRST line to delay the reset signal and allow VDD to stabilize.

I will provide an update once we confirm if this resolves the communication issue.

DS90UB948-Q1: Unused input pin

Shuji Ishiwata — Sun, 10 May 2026 23:38:30 GMT

Part Number: DS90UB948-Q1
Other Parts Discussed in Thread: DS90UB947-Q1,

Hi All,

I have some questions about the DS90UB947-Q1 and DS90UB948-Q1.

1) If I don't use RIN1– / RIN1+ on the DS90UB948-Q1, is it okay to leave it open?

2) For the openLDI input on the DS90UB947-Q1, is it okay to pull down unused input pins to GND?

Best Regards,
Ishiwata

TUSB1310A: TUSB1310A power up flow

Kfir Tito — Sun, 10 May 2026 14:48:29 GMT

Part Number: TUSB1310A
Other Parts Discussed in Thread: TPS65000

Dear Team,

I'm using TUSB1310A as a USB3 PHY device connected to a host (PC) and driven by a link layer - Synopsys controller IP over an FPGA device.

Currently, I do see my XTAL 40MHz but I don't see PCLK toggling after RESETN is released.

OUT_ENABLE is connected to pin PG_N at TPS65000 (step-down converter that generates 1.8V and 1.1V from 3.3V input) according to the reference design: 6724.superphy_usb_b_ulpi_1205.pdf

Board straps configurations: (using 4.7K PU/PD resistors) - also measured with a scope:

PIPE_16BIT (PHY_STATUS) = 0 (PIPE MODE ON)
XTAL_DIS (RX_ELECIDLE) = 0 (XTAL)
REFCLKSEL1:0 (ULPI_DATA5:4) = 11 (40MHz)
ULPI_8BIT (ULPI_DATA6) = 0 (ULPI MODE OFF)
ISO_START (ULPI_DATA7) = 0 (PIPE ISOLATE MODE OFF)
SSC_DIS (TX_MARGIN0) = 0

Need your support with a few questions:

1. For USB3 (PIPE) - is the ULPI connection also required? Is it mandatory for chip power-on? (Is ULPI reset necessary for PIPE to be ready?) Must the link layer contain a ULPI I/F?
2. Is OUT_ENABLE implemented correctly? Is it okay that OUT_ENABLE will rise with 1.8V (VLDO1)?

DP83867IS: 10MBit packet loss with SGMII PHY TX

Jochen Baltes Jochen Baltes — Fri, 08 May 2026 15:13:53 GMT

Part Number: DP83867IS

We are using the PHY in two different circuits on our switch. We have two 10/100/1000 Mbit interfaces on the front panel: one connected to the CPU and one to the switch.

The CPU interface works flawlessly, but unfortunately the switch interface does not.

In 10 Mbit mode, between 30 and 50 per cent of packets are lost. These are the received packets.

We assume that packets are being lost between the PHY and the switch (PHY TX -> SW RX).

The PHY is connected to the switch via the SGMII interface. We have looked at the datasheet again and found the ‘10M SGMII Configuration’ register. There is a bit 7, 10M_SGMII_RATE_ADAPT. Data sheet Rev. A states: ‘Clear this bit to enable 10M SGMII operation.’ The latest data sheet states: ‘RESERVED – Do not change this bit. The PHY automatically adapts to 10M speed.’ If we set the bit to ‘0’ before a test, the test runs without errors. If we set the bit back to 1, the errors reappear. Can we set the bit to 0 for 10-bit traffic, or is there a reason not to do so? Why does the datasheet say ‘Reserved’?

The PHY connected to the CPU runs without errors. It runs under Linux, and the Linux driver sets this bit to ‘0’ for 10Mbit.

DP83826I: DP83826I phy not getting up with IMX93 processie

Himanishu Karadbhajne — Fri, 08 May 2026 14:05:57 GMT

Part Number: DP83826I

Hello

We are using DP83826IRHBR with IMX93 processor

Below device tree entry

&fec {
        pinctrl-names = "default", "sleep";
        pinctrl-0 = <&pinctrl_fec>;
        pinctrl-1 = <&pinctrl_fec_sleep>;
        phy-mode = "rmii";
        phy-handle = <&ethphy1>;
        snps,clk-csr = <6>;
        status = "okay";        mdio {
                compatible = "snps,dwmac-mdio";
                #address-cells = <1>;
                #size-cells = <0>;                ethphy1: ethernet-phy@0 {
                        compatible = "ethernet-phy-ieee802.3-c22";
                        reg = <0>;
                        pinctrl-0 = <&pinctrl_eth1>;
                        reset-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
                        reset-assert-us = <10000>;
                        reset-deassert-us = <80000>;
                };
        };
};

getting below error logs

[ 1.963513] fec 42890000.ethernet: Invalid MAC address: 00:00:00:00:00:00
[    1.970314] fec 42890000.ethernet: Using random MAC address: 56:b0:d4:15:89:a7
[    1.978861] mdio_bus 42890000.ethernet-1: MDIO device at address 0 is missing.
[    1.986766] fec 42890000.ethernet eth0: registered PHC device 0
[   15.078672] fec 42890000.ethernet eth0: Unable to connect to phy

Pin details

MODESELECT - GND
COL - 1.8 V
CRS - NC

TX_D0 - ENET2_TX_D0 (processor pin)
TX_D1 - ENET2_TX_D1 (processor pin)
TX_D2 and TX_D3 - NC
TX_CLK - NC

RX_D0 - ENET2_RX_D0 (processor pin)
RX_D1 - ENET2_RX_D1 (processor pin)
RX_D2 and RX_D3 - NC
RX_CLK - NC

Can you please help

TXU0304: TXU0304 OE input internal pulldown resistor value

Csaba Kisházi — Fri, 08 May 2026 13:23:36 GMT

Part Number: TXU0304

Hello, can you provide the value of the internal pulldown resistor on the OE line?
It is not provided in the datasheet.

DP83826AE: [Hanwha Vision] Inquiry about DP83826AE

Jamie LEE — Fri, 08 May 2026 13:09:12 GMT

Part Number: DP83826AE

Hi experts,

Could you provide information on the compatibility of the DP83826AERHBR with other PHY ICs?

I'm specifically looking for any documented interoperability issues with same-vendor or third-party PHYs, as well as any available test results.

Thank you!

Regards,

Jamie

DP83822IF: 100ms errors during ESD testing

Huang Feng — Fri, 08 May 2026 09:50:47 GMT

Part Number: DP83822IF

Hello,

During contact discharge testing (as part of the IEC 61000-4-2 ESD immunity test) on an SFP optical module paired with the DP83822IF PHY, I have intermittently observed bit errors lasting approximately 100 ms.

Software analysis:
When the PHY chip is reset, the CPU continues transmitting and receiving data. During this reset period, the received data does not match the transmitted data, and this mismatch is also counted as a bit error.

Investigation so far:
I found that the Deep Power Down function – a dedicated term from the DP83822IF datasheet – has a duration of exactly 100 ms. This suggests that the test interference may be triggering the Deep Power Down mode. However, after I adjusted the Deep Power Down Speed register to 50 ms and repeated the test, the bit error duration remained 100 ms.

Questions:

1. What other mechanisms of this PHY chip could cause this 100 ms bit error phenomenon during contact discharge ESD testing?

2. If the Deep Power Down function is indeed the root cause, is there a way to completely disable it?

Background context:
Our communication link includes filtering, so losing one or two packets during the test would not be a major issue. However, a continuous 100 ms data loss is considered a serious failure.

Thank you for your assistance.

DP83822I: Packet alignment and preamble length

Dom — Fri, 08 May 2026 07:35:51 GMT

Part Number: DP83822I
Other Parts Discussed in Thread: DP83826AI,

Dear support team,

the microcontroller we're planning to use has an Ethernet MAC with specific requirements regarding the packet alingment and preamble length, limiting the number of interoperable PHYs.

In 10 MBit mode the MAC requires the packet to be octet-aligned. It cannot handle packets correctly if the preamble has been shortened, leaving the packet non-octet-aligned. Also it requires a preamble length of at least 1 byte.

Additionally the PHY needs to meet the EtherCAT requirements. We first planned to use the DP83826AI but due to external contraints we have to switch to a current mode PHY.

Does the DP83822I comply with these requirements?

Thank you

TCAN5102-Q1: Response Time of the TCAN5102-Q1

Hiroki Matsumoto — Fri, 08 May 2026 07:21:05 GMT

Part Number: TCAN5102-Q1
Other Parts Discussed in Thread: TCAN4572-Q1

I could not find this information in the datasheet, so I would like to confirm.

Is the TCAN4572-Q1 required on the commander side? Are there any limitations if the TCAN4572-Q1 is not used?

How long does it take for the responder to reply after the commander sends a write/read request? Does it vary depending on the CAN FD communication speed?

DP83822H: Not able to establish 100 Mbps link.

Ajul P — Fri, 08 May 2026 05:05:57 GMT

Part Number: DP83822H

I have to configure DP83822H with my PIC32CX1025SG41128. Magnetic transformer used in design is HX1188NL. I have done the basic strap configurations for strap resistors and link is up for 10mbps full duplex. Autonegotitaion is happening for 10mbps & 100mbps from PHY side which is confirmed by reading registers values from Phy. But 100Mbps is not working. Even the 10mbps link is not stable with all laptops, but stable with D-link switch. I will share my schematics details for reference.

Anyone have idea what is the problem here? Wether it is physical link issue or software issue?

NOTE: All resitor network values made DNP for MII Mode. 25MHz clk generated from MCU and given. Final out is given to a molex connector not RJ45.

SN75DP120: Continued Use of the SN75DP120

ttd — Fri, 08 May 2026 00:18:00 GMT

Part Number: SN75DP120

We have been using the SN75DP120 up until now. Would it be acceptable to continue using the SN75DP120 for our new development projects? I looked into whether there were any new products available, considering supply status and end-of-life (EOL) factors, but I could only find the new 4-channel TDP series. Therefore, we are considering continuing to use the SN75DP120.

FAN31790: CLKOUT OF A FAN31790 CONNECTED TO XTAL1 OR XTAL2 OF A SECOND FAN31790

Michael Way — Thu, 07 May 2026 21:50:56 GMT

Part Number: FAN31790

In a system with more than one FAN31790, can CLKOUT be used to drive the XTAL input of a second FAN31790? If so, would that be XTAL1 or XTAL2?

DS250DF230: CDR not locking and raw bypass is not working

Luke Korte — Thu, 07 May 2026 15:01:59 GMT

Part Number: DS250DF230
Other Parts Discussed in Thread: DS280DF810

So a bit of background, I have a board that uses a DS280DF810 and a DS250DF230 which have 5 channels of 10GE ethernet.
They both have the same electrical design, with some small changes, namely the DS250DF230 has external AC coupling caps.
The DS280DF810 is working on all channels while I am struggling to get the CDR to lock on the DS250DF230.
Even more weird is that the DS250DF230 does not output anything even when I set the drivers to output raw data when the CDR is not locked.
I have also checked that the diff signals are reaching the DS250DF230. I tried bypassing the chip with wire mods and removing the chip. This works and I can see the data come through.

Here is what I write to all the channels for the DS250DF230.
I am using the refclk_out from the DS280DF810 as the refclk_in (i.e. 25MHz).

#modify_reg(address, data, mask)
modify_reg(0xfc, 0x01, 0xff)
modify_reg(0xff, 0x03, 0x0f)
modify_reg(0x00, 0x04, 0x04)
modify_reg(0x0a, 0x0c, 0x0c)

#manually set data rate to 10.31250 Gbps with 25MHz clk
modify_reg(0x60, 0x90, 0xff)
modify_reg(0x61, 0xb3, 0xff)
modify_reg(0x62, 0x90, 0xff)
modify_reg(0x63, 0xb3, 0xff)
modify_reg(0x64, 0xff, 0xff)
modify_reg(0x09, 0x04, 0x04)
modify_reg(0x18, 0x10, 0x70)
modify_reg(0x2f, 0x00, 0x04)

modify_reg(0x31, 0x20, 0x60)
modify_reg(0x1e, 0x08, 0x08)
modify_reg(0x1e, 0x00, 0xe0) #set output to raw when CDR is not locked
modify_reg(0x3d, 0x80, 0x80)
modify_reg(0x3d, 0x00, 0x40)
modify_reg(0x3f, 0x40, 0x40)
modify_reg(0x3e, 0x40, 0x40)
modify_reg(0x3d, 0x0f, 0x1f)
modify_reg(0x3f, 0x00, 0x0f)
modify_reg(0x3e, 0x03, 0x0f)
modify_reg(0x0a, 0x00, 0x0c)

Some feedback from registers
read(0xef) 0e
read(0xf0) 01
read(0xf1) 15
read(0xfe) 03

read(0x01) for channel 0 = c0
read(0x01) for channel 1 = 80

I have confirmed that removing the ethernet signal clears bit 7 of 0x01.
I am not sure the meaing of bit7.

read(0x02) for channel 0 = 01
read(0x02) for channel 1 = 01

This tells me the data rate of the signal is below the min VCO.
But I am still confused that nothing is coming through with the raw data enabled.

My question is, what registers can I look at to try and diagnose the problem?
Why is the raw data mode not working?
Is it possible that I must use a 30.72MHz clock and use the default clock settings in reg 0x2f?

Any suggestions would be much appreciated.

Thank you

TUSB9261: TUSB9261 Firmware Programming Through Linux

Muhammed Shajih Kakkattil — Thu, 07 May 2026 14:43:33 GMT

Part Number: TUSB9261

Hello,

I am looking to program my TUSB9261 using Linux over USB. I saw in the E2E forum that the appropriate files can be sent over via PM. Would you be able to send the Linux driver file and provide instructions on how to install and set it up?

Thanks,

Muhammed

ONET8551T: ONET8551T spice model

Ayanami Kate — Thu, 07 May 2026 12:33:50 GMT

Part Number: ONET8551T

Hi,

I was unable to locate the SPICE model for the ONET8511TY on the TI official website. Therefore, I am writing to kindly request if you could provide the SPICE model (or macro model) for this specific chip.

In addition, I would like to know if there is a SPICE model for ONET8511T. I could not find this chip on the website.

Thanks.

ADS131M04EVM: Unable to read and write the registers.

Shreya R J — Thu, 07 May 2026 12:32:25 GMT

Part Number: ADS131M04EVM
Other Parts Discussed in Thread: ADS131M04

Hi,
I have connected the ADS131M04 ADC to a Raspberry Pi, with the ADC powered from the RPi supply. I am trying to read and write registers over SPI, but I am consistently receiving 0x050F or 0x0500 as the response word, which appears to be the STATUS register instead of the expected response.

SPI config:
1. Using "pigpio" to interact with gpios
2. SPI_bus: 0,
3. SPI_dev: 0
4. Baud rate: 8 Mhz

read_register:
1. Build RREG command
2. FRAME 1 → send RREG command
3. FRAME 2 -> Read response
4. Parse response

write_register:
1. Build RREG command
2. Add register data words
3. Pad remaining words to complete frame
4. FRAME 1 → send WREG command + data (5 word frame)
5. FRAME 2 → Read WREG response

Observed issue:
Instead of valid responses, I consistently receive: 0x050F or 0x0500
This appears to be the STATUS word
Suggests the ADC is continuing to output conversion data or the command is not being recognized.
Kindly help me with the right init sequence for this.

Attaching the file used:
adc.txt

AM261-SOM-EVM: AM261x enet_lwip_cpsw example hangs after warm reset – works only after power cycle

Akshay Sidral — Thu, 07 May 2026 10:31:48 GMT

Part Number: AM261-SOM-EVM

Hello TI Team,

I am working with AM261x and testing the enet_lwip_cpsw example from MCU+ SDK.

The application works correctly after power-on and Ethernet communication is successful. However, after resetting the board, the application no longer boots correctly and only prints a long hexadecimal dump on UART.

Example UART output:

000002010100000000000100414d323631580000000000000400cdab0000010001000000000000000000000000000000000000001aefc36abc625f8da980be8cd275a58eb77c6b83fc91c7548a793be4c020c2cded676ddf26b3db6361bf5fc01d7f3e71abc5cfc2b0ce553497c36284fa66dfbd00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000f065c5297cfdc2c3882241850b4d3be1ba0804935a1a554ad09c09035621c40e6ba5c61056f45e282a50f115612f609b7858836916a1707f426f8aaed4068518CC

After this, the board hangs and the application does not execute.

The only way to recover is:

remove power completely
power ON again

Then the application works normally again.

I also noticed the SDK documentation states:

“If you need to reload and run again, a CPU power-cycle is MUST”

However, for a production device, the system must recover automatically after:

watchdog reset
warm reset
brownout/power fluctuation
software crash

without requiring a complete power removal.

I suspect:

CPSW/UDMA/PHY state is not getting reset properly during warm reset
OR
external PHY / OSPI remains in stale state after reset.

I also checked the AM261x reset architecture documentation which shows separate PORz and warm reset paths.

Questions:

Is this a known limitation of the enet_lwip_cpsw example only, or of the AM261x Ethernet subsystem itself?
What is the recommended production-grade reset sequence for CPSW + lwIP?
Is there an official Ethernet deinitialization/shutdown sequence before reset?
Is external PHY reset mandatory during warm reset?
Does TI recommend using POR reset instead of warm reset for Ethernet recovery?
Is there any known issue related to OSPI reset during software reset on AM261x? I saw the datasheet mentions special handling for OSPI flash reset.
Are there any reference examples showing successful repeated open/close/restart of CPSW/lwIP without requiring power cycle?

Environment:

Device: AM261x
SDK: MCU+ SDK (mcu_plus_sdk_am261x_26_00_00_01)
Example: enet_lwip_cpsw
Board Version: E2

Any guidance for implementing a robust production-grade recovery/reset architecture would be very helpful.

BR,
Akshay

TPD1E0B04: SD107WS-7-F

prajesh p — Thu, 07 May 2026 10:24:37 GMT

Part Number: TPD1E0B04

Please suggest an alternative Texas Instruments part for the SD107WS-7-F. The form factor and specifications should be the same, and it should be a drop-in replacement part.

DP83869HM: Link loss pass-through: how to detect if copper or fiber side has link loss in media-converter mode

Walter Ahrend — Thu, 07 May 2026 09:47:41 GMT

Part Number: DP83869HM
Other Parts Discussed in Thread: DP83869

DP83869 is used in media converter mode (copper/fiber) and link loss pass through is enabled.

In case a link loss is detected, how can the user detect which side caused the link loss?

Is there a register that can be read by the user that indicates which side caused the link loss?

Best Regards,

Walter

LMH1228: Defining IN/OUT pins

Luc meijer — Thu, 07 May 2026 09:28:22 GMT

Part Number: LMH1228
Other Parts Discussed in Thread: LMH1208, LMH1297

I have a question regarding the LMH1208/LMH1228.
There are several configuration pins to define the input/output path for video. When a path is defined, can the other pin be left floating?
Example: OUT0_SEL=H, SDI_OUT2_SEL=L; this will put the device in Dual cable drivers mode. Can we leave the host side loop-back OUT0p/n be left floating, or do you recommend defining these pins.

Same question regarding the LMH1297, if we configure SDI_IO as input and OUT0 as output, can we leave SDI_OUT floating?

AM625: Over- and undershoot on eMMC signals

Niels Ole Jorgensen — Thu, 07 May 2026 08:47:40 GMT

Part Number: AM625
Other Parts Discussed in Thread: CSD

We have made a new product serie with the AM6254 microprocessor. As flash memory we have chosen an eMMC from Macronix, attached to the MMC0 channel on the AM6254.

During read from the eMMC we are seeing some over- and under-shoot on the data signals, where the values are just on or above the limits (Figure 7-1 in the AM625 datasheet) for the MMC0 pins.

The attached oscilloscope picture shows eMMC.Data3 measured as close to the AM6254 as possible.

The over shoot voltage level is measured up to 2.25 V, and under shoot level down to -0.34 V. The over and under shoot time is measued to totally 2.6 ns out of 10 ns period time.

So levels are just on / above limits. (High level: 1.8 V + 20% = 2.16 V; Low level: -0.36 V, Time 20% of 10 ns = 2 ns)

How concerned should we be regarding the levels of the over- and under-shoot??

We have tried to lower the driver strength of the Macronix eMMC, but haven't succeded.

According to Macronix MX52LM08A11 datasheet the eMMC should support different driver strengths:

We are running HS-200 mode, so we would like to test the 0x2 (66 ohm) settings, instead of the default 0x0 (50 ohm).

As far as we read the JEDEC specification the driver strength should be set in the HS_TIMING [185] of the Extended CSD registers:

We have tried to change the settings of this register, but we haven’t succeeded.

We are using u-boot and in the device tree for the board in u-boot, we have changed the driver strength for the eMMC controller, just like U-Boot examples shows for the AM62xx processor.

We have used the mmc command in u-boot, but as far as I can see in u-boot 2026.01 version source code, there is no command to set the driver strength via the mmc command only read the status of it.

Do you have any example of how we can set the driver strength in the eMMC via u-boot?

Best regards

Niels Ole Jørgensen

DEIF A/S

ONET8501T: ONET8501T Spice Model

Ayanami Kate — Thu, 07 May 2026 08:21:37 GMT

Part Number: ONET8501T

I was wondering if you have spice models or something similar which I could use to simulate this device?

DS125DF1610: ds125df1610 profile updeter

Oliver Smith — Thu, 07 May 2026 07:33:30 GMT

Part Number: DS125DF1610

Hello Team, Where can you get the updater.exe to use DS125DF1610 with SigCon Architect ?