Interface forum - Recent Threads

DS90C363B: DS90C363B CLK PLL and TxCLKout duty Cycle

Eric Mac — Sat, 07 Nov 2026 17:05:35 GMT

Part Number: DS90C363B

For the DS90C363B internal CLK PLL, is it an edge detect type where the output CLK (TxCLKout) duty cyle does NOT track the input CLK (TxCLKin)? Then what is the output CLK duty Cycle? Does figure 12 in datasheet hints at that it maybe 4/7 hi (57%) and 3/7 43% low?

TCAN3404-Q1: Specification of CAN Bus Wake-Up Pattern for TCANC340x-Q1

Mizumoto Ayaka — Sat, 07 Nov 2026 08:14:07 GMT

Part Number: TCAN3404-Q1

According to the TCANC340x-Q1 datasheet, the device can detect a valid wake-up pattern on the CAN bus while in standby mode and signal the MCU through the RXD pin.

Could you please clarify the specification of the valid wake-up pattern detected by the TCANC340x-Q1?

Specifically, we would like to know:

What CAN bus signal sequence is recognized as a valid wake-up pattern?
Where is this wake-up pattern specification described in the datasheet or other documentation?

SN75LVDS83B: Overshoot and Undershoot on LVDS clock and data signals

kadam shah — Sat, 07 Nov 2026 07:35:58 GMT

Part Number: SN75LVDS83B

Hello Team,

We have developed custom board using SN75LVDS83BDGGR On LVDS clock and data signals we are observing higher amount of overshoot and undershoot.

Can you guide us how to remove overshoot and undershoot from signals?

I have attached clock waveform for referance.

Thanks

TUSB1021-Q1: TUSB1021-Q1 Eye Diagram Testing

Ryan Kitto — Fri, 06 Nov 2026 19:17:21 GMT

Part Number: TUSB1021-Q1

TUSB1021-Q1 Eye Diagram Testing Results:

DP83TD530-Q1: What are the waveforms on TX and RX pin?

yufeng.zhang — Fri, 06 Nov 2026 09:05:51 GMT

Part Number: DP83TD530-Q1

Hello, TI expert,

We are applying DP83TD530-Q1 in our design and meet the communication issue.

I apply oscilloscope to measure waveform on DP83TD530-Q1 TX pin. The signal is sent from MCU on the board. I found some waveforms whose frequency are much higher than 12.5MHz. I am confused what on earth waveforms on TX and RX.

Could you send some measured results or figures for wavefroms?

Thanks a lot.

TCAN6062-Q1: ResXL bit and stabilization time,

종길 임 — Fri, 06 Nov 2026 09:01:37 GMT

Part Number: TCAN6062-Q1
Other Parts Discussed in Thread: TCAN6062

Hello Experts,

Could you please help these several questions?

I have a question about the transceiver, as follows.You stated the following about FAST mode:

“When the TXD pin is LOW for at least tSELECT, FAST TX mode becomes pre-selected. After this pre-selection, two valid consecutive low-to-high rising edges on TXD within tSymbolNom will cause the device to transition to FAST TX mode.”

I mapped this process to the CAN XL frame as shown below:

We have the tSELECT requirement as shown below:

Based on my mapping picture, should we hold the resXL bit for longer than 500 ns so that the transceiver can become pre-selected? Is that correct?This is because, at the ADH bit, CAN XL starts generating PWM, where there are two valid consecutive low-to-high rising edges on TXD within tSymbolNom.

for the second question:

If CAN XL generates a frame as shown in the preceding picture, after tSELECT, the transceiver becomes pre-selected. If, at T1, it detects one rising edge (a pulse like the one shown at T1 in the picture), and then the time exceeds tSymbolNom (205 ns) before another valid rising edge occurs (still can not detect the second valid rising edge), is the transceiver still in the pre-selected state?

If not, will the PWM starting from T4 (two valid consecutive low-to-high rising edges) not be detected, and will the transceiver still operate in normal mode with NRZ encoding? Can it still switch to FAST mode?
Do we need to hold TXD at level 0 for tSELECT again so that the transceiver can return to the pre-selected state?
Is there any way for the transceiver to remain in the pre-selected state in this case and still detect the two valid consecutive low-to-high rising edges at T4 and switch to FAST mode?

SN65DSI84-Q1: SN65DSI84TPAPRQ1 IBIS Model

Jingkun Wang — Fri, 06 Nov 2026 07:25:36 GMT

Part Number: SN65DSI84-Q1

Hello TI Team,

Could you provide the IBIS model of SN65DSI84TPAPRQ1 for us?

We want to do the SI simulation.

Best Regards!

Wang Jingkun

SN65DSI83: SN65DSI83 - flickering issue on complete setup

Katarzyna Stepien — Fri, 06 Nov 2026 07:21:31 GMT

Part Number: SN65DSI83

We are a manufacturer of display modules. In our module, which utilizes a TI SN65DSI83 bridge, the screen flickers upon power-up or when waking from sleep mode—though this does not happen every time.
We would appreciate your support in identifying the root cause of this issue. We are unsure whether the problem lies within the IC itself or our bridge configuration.

Here is what we have determined so far:
• Adjusting the display timings resolved the flickering in 3 out of 6 faulty modules; however, the issue persists in the remaining 3.
• There is no flickering when the bridge operates in test mode; it only occurs during normal operation.
• X-ray inspection revealed no soldering defects on the bridge.

We kindly request:
1. An assessment of whether our bridge configuration is correct.
2. Guidance on what further checks we should perform to identify the cause of the issue.

P82B96: Mutli-drop I2C slaves on high capacitance bus

AhmadBashar Taji — Fri, 06 Nov 2026 07:17:34 GMT

Part Number: P82B96

Hello,
I have a relatively high capacitance I2C bus (below 4nF) and I need to connect several I2C slaves in a distributed manner.
I am thinking about using P82B96 as an interface between the I2C master/salves and the high capacitance bus (as shown below), but I cannot find whether it is okay to connect several P82B96 on the Tx/Rx and Ty/Ry side.

is this configuration okay?

DS90UB941AS-Q1: DS90UB941AS-Q1 → DS90UB928-Q1 not working

Yuan Ji — Fri, 06 Nov 2026 06:29:51 GMT

Part Number: DS90UB941AS-Q1
Other Parts Discussed in Thread: TDA4VM

Hi TI,

I'm using TDA4VM EVM board(J721e) to drive on-board ub941 and 1280×720 display panel (with ub928).

What works (same hardware, same coax, same panel):

928 internal pattern generator → full white on panel. LVDS + panel path OK.
941AS internal pattern generator through the FPD-Link → full white on panel (PCLK 66.7 MHz). LOCK solid, 928 link error counter stays at ~3. FPD serializer, coax, 928 FPD receiver, and panel are all proven at this pixel rate.
DSI reception on the 941AS is clean:
- DPHY_STATUS = 0x13 (clock lane + D0/D1 detected)
- DLANE0–3_ERR = 0x00, CLK_LANE_ERR = 0x00
- VC_DTYPE = 0x3E (receiving RGB888 video packets)
- DSI_FREQ = 0x4B (75 MHz — exactly our pixel clock)
- Auto M/N settles at M=1/N=3 → measured PCLK 75 MHz
- 928 side: LOCK = 1, PCLK counter ≈ 75 MHz, link error count ~3

What fails: selecting the DSI input (PG off) → panel stays black. 941AS DSI_STATUS (0x28) = 0x05: FPD3_ERR (bit4) persistent + EOT_ERR (bit2, sticky from early bring-up). FPD3_ERR never clears while DSI input is active.

Questions:

Datasheet §8.4.6.1 states single-link mode is compatible with DS90UB926-Q1/928-Q1 at ≤85 MHz. Our PCLK is 75 MHz and the PG path proves the whole link works at this rate. Are there additional conditions for DSI pass-through (as opposed to internal PG) to a Gen1.5 deserializer — or a known errata for this combination?
What exactly does a persistent FPD3_ERR indicate when the DSI RX reports zero errors and all four DUAL_STS status bits are set? Which domain does this flag (DSI→FPD FIFO? FPD TX?), and what is the recommended debug sequence?
Is there a reference register sequence for 941AS (2-lane DSI, RGB888 video mode, continuous clock, DSI-ref mode) → 928 pass-through that we can diff against? We already diffed against the §8.4.5.3 example (which is 4-lane / independent 2:2).
Sanity check: for fDSI = 450 MHz, Eq. 14 gives TSKIP_CNT = Round(65×0.450−5) = 24 → register value 0x30. Correct?

TCAN1044-Q1: supply Characteristics

QIN LEI — Fri, 06 Nov 2026 05:06:22 GMT

Part Number: TCAN1044-Q1
Other Parts Discussed in Thread: TCAN1044A-Q1

hello i have one qestion about the TCAN1044,I Checked the datasheet,the folowing pciture

i think the max current is 80mA on the normal operationg mode

i also check TI user'guide about the TPS929240, the VLDO pin(MAX 80mA) to supply to the CAN TR,

it is ok?

How can I determine the maximum current consumption of the transceiver in an actual application?

please give me your advice

thank you

PCA9544A: Regarding Voltage PU and VIH of PCA9544APWR

Balkis M — Fri, 06 Nov 2026 04:52:53 GMT

Part Number: PCA9544A

Hi Team,

Am Looking at PCA9544APWR datasheet and observe that two different volatge details for I2C (Input).

In Table 5.1, it says Input I2C voltage rage depends on associated data line ref voltage, where as in section 6.3, VIH is 0.7xVCC, which is 2.31V if my VCC is 3.3V. How can I connect I2C line from master which is 1.8V?

Regards,

Balkis

ESDS552: Recommended ESD protection circuit for RS-485

Hiromu Susami — Fri, 06 Nov 2026 01:09:58 GMT

Part Number: ESDS552
Other Parts Discussed in Thread: ISOW1432

Hi team,

Can we use only ESDS552 IC for ISOW1432DFMR without any addition protection circuit as we don’t want to add complexcity? I am concerning about that the clamp voltage exceeds the +15V bus-pin abs max of the ISOW1432DFMR. If not, could you tell me recommended parts and circuit?

Target is IEC Standard IEC 61000-4-2, +/4kV contact discharge and +/-8kV air discharge.

Regards,
Hiromu

SN65DSI83: DSI input package HSS to HSE time requirement

PYTsai — Fri, 06 Nov 2026 00:27:44 GMT

Part Number: SN65DSI83

My customer encounter an issue when HSS to HSE time too short, we will see CHA_SYNCH_ERR report error.

increase the HSS to HSE duration from 2B to a higer value the issue soled.

can yuo advise the minimum requrie HSS to HSE duration ?

TLK1221: Question about TLK1221

Jimmy Huang — Thu, 05 Nov 2026 16:10:48 GMT

Part Number: TLK1221

Hello:

The following is a schematic diagram of TI's TLK1221 application. The core intention is to convert DP's AUX differential signal into a single ended signal, and then transmit it through optical fiber. The AUX speed is 1Mbps. Please help confirm whether the chip can achieve this function. Thank you!!!

TCA9548A: TCA9548ARGER Failure at ICT station as Short

Ortiz Gatica — Thu, 05 Nov 2026 14:51:04 GMT

Part Number: TCA9548A

FAR-AR2608-CIE.pdf

Attached you can see the FAR provided by our team for following this case.

Unit fails ICT, displaying the following paperless report

As can be observed, U2 is the defective component, as the ICT expects an open circuit but detects
unexpected impedance across the signals routed to U2, We measured the signal and found attenuation across the component between pin 4 to pin 8 on the device, the measure is 0.46487Kohms and We compared it against a known-good board that passed ICT the date is 6.1097Mohms. See the FAR attached.

TCAL9539-Q1: I2C spiketime

Bingyun Yang — Thu, 05 Nov 2026 12:21:12 GMT

Part Number: TCAL9539-Q1

Hi team,

Our customer is designing cockpit with our TCAL9539-Q1.
When the SCL signal is low, the SDA signal has a spike lasting 360ns. This duration exceeds the 50ns I2C spike time specified in the datashett.

But since SDA is low at this time, it probably won't affect the signal.

Since this spike occurs at the 9th clock cycle, we suspect it might be caused by voltage fluctuations during the transient switching between the master and slave in I2C communication.

I'd like to know if this spike has any potential risks, and if we want to reduce it, are there any specific measures we can take? Could you please help to give some advice? Thanks!

Best Regards,
Bryn Yang

TLK10232: TLK10232CTR lifecycle and production-status confirmation for new design

Nidhi Sharma — Thu, 05 Nov 2026 11:17:30 GMT

Part Number: TLK10232

We are evaluating the TI TLK10232CTR for use in a new telecom/networking product, specifically as a dual-channel XAUI-to-SFI interface for two 10G SFP+ ports.

TI.com currently lists TLK10232 as ACTIVE. Before approving this component for our new design, we would appreciate written confirmation of the following:

Is TLK10232CTR currently in active production, rather than being supplied primarily from existing finished-goods or die inventory?
Is TLK10232CTR recommended by TI for a new design entering production in 2027?
Is there currently any planned or anticipated NRND, Last-Time-Buy, Product Withdrawal, or EOL activity for TLK10232CTR?
What production/longevity horizon should we reasonably plan for this device?
We typically require approximately a 10-year product availability horizon for telecom designs. Is TLK10232CTR appropriate for that requirement?
Does TI have a newer recommended device for dual XAUI-to-SFI/SFP+ applications that offers a better long-term lifecycle position?

If possible, please have the High-Speed Interface product line/product marketing team confirm the lifecycle information above.

Thank you,

Nidhi Sharma
Senior Hardware Designer

TCA39306: Can I use this device for I2C Interface Level Shifting (1.2V to 1.8V) Bidirectional?

RAJ KUMAR — Thu, 05 Nov 2026 10:33:44 GMT

Part Number: TCA39306
Other Parts Discussed in Thread: LSF0102

Hi,

I am using the TCA39306DCUR as an I²C level translator between Agilex-PL (1.2 V) and HPS (1.8 V).

However, the datasheet includes the following note:

"To support translation, VREF1 supports 0.85 V to VREF2 − 0.6 V. VREF2 must be between VREF1 + 0.6 V and 5.5 V."

In my application, VREF1 and VREF2 are operating at the boundary conditions of the specified voltage ranges.

Could you please clarify whether the device will operate reliably under these conditions? Specifically, would minor voltage variations due to PCB IR drop or supply ripple (approximately 20–25 mV on either VREF1 or VREF2) affect the level translation functionality or violate the specified operating conditions?

Best Regards,
Raj

ards,

Raj

DP83822I: Some of the DP83822I PHYs have poor MDI compatibility. Some network ports can be recognized while others cannot.

Yang RuoFei — Thu, 05 Nov 2026 09:04:23 GMT

Part Number: DP83822I

Some of the DP83822I PHYs have poor MDI compatibility.

the bad DP83822I PHY device ports can be recognized by some device, and some of device can not be recognized. the other devices did not use the DP83822I PHY.
the bad DP83822I PHY device connect a good DP83822I PHY device, the link can be recognized,
the bad DP83822I PHY show the auto negotiation is not success. and MDI became to MDIX due to the AMDI_EN feature.

when I exchange the IC on the bad and good board, the failure follow the IC.

please help me to analyze this issue.

TPS62869EVM-118: GUI interface of theTMP62869 cannot be connected

BH goh — Thu, 05 Nov 2026 08:07:21 GMT

Part Number: TPS62869EVM-118
Other Parts Discussed in Thread: TPS62869, USB2ANY,

Hi, previously the USB2ANY module is working fine with the I2C wire connections to the target TPS62869 DCDC chip. However, I saw there is a Software for USB2ANY explorer and loaded the software. The software requested a older 2.7.0.0 FW to be downloaded. So my previous FW get overwritten and I forgot what is the version and also can't find from TI website. Question, can this 2.7.0.0 use. I managed to see the GUI but the I2C like can't get the data so cannot be connected. Please help

DS90C187: Availability of this IC and proposals for substitutes

R.Fukunaga — Thu, 05 Nov 2026 07:30:24 GMT

Part Number: DS90C187
Other Parts Discussed in Thread: SN65LVDS93B-Q1, DS90C189-Q1, SN65LVDS93A-Q1, DS90UB948-Q1

Hi all,

We are considering adopting this IC.
When I checked the data sheet, it says the product was released in 2012, so I think it is a little old product.

DS90C187 Low Power, 1.8-V Dual Pixel FPD-Link (LVDS) Serializer datasheet (Rev. C)
Do you have any recommended FPD-Link product as an alternative to this product?

Best Regards,

Ryusuke

LMH0384: Inquiry regarding minimum input voltage swing for LMH0384SQE/NOPB

Noriyuki Takahashi — Thu, 05 Nov 2026 07:27:27 GMT

Part Number: LMH0384

Hi team,

They am evaluating the LMH0384SQE/NOPB for an HD-SDI (1080p30) application. Considering the device's equalization capabilities, could you provide the minimum input voltage swing (in mVpp)?

Regards,

Noriyuki Takahashi

DP83869HM: termination resistors on SIN, SIP

visweswara rao kalla — Thu, 05 Nov 2026 06:58:20 GMT

Part Number: DP83869HM
Other Parts Discussed in Thread: DP83869

I have interfaced DP83869HM with AFBR-59E5APZ , question is I have termination resistors external on the board connected to SIP , SIN terminals of DP83869HM. is it good have external ?

can i remove since DP83869HM has internal termination.

thanks

visweswara.

TUSB1044A: TUSB1044A GPIO configuration

Janne Lesonen — Thu, 05 Nov 2026 06:56:41 GMT

Part Number: TUSB1044A

Hi,

We are planning to utilize TUSB1044A as a new re-driver component. We ended up to select this specific IC due to comprehensive configuration options through GPIO and bootstrap pins, without the direct need for I²C configuration/control.

What I’m requesting is to verify, whether the utilized configuration is correct, when using the re-driver in device side, between Device’s processor and Type-C connector facing towards host-PC. We are also utilizing a separate PD- controller that handles the CC-lines, thus being able to control TUSB1044A’s flip pin. In our product, the device processor is connected to U[T/R]X pins [9,10,12,13,15,16,18,19] and the Host facing type-c connector is connected to D[T/R]X pins [30,31,33,34,36,37,39,40]

Configuration:
USB3.2 only, SWAP=L
DIR1 = ”L”
DIR0 = ”H”
CTL1 = ”L”
CTL0 = ”H”

Have we understood correctly that now, from our device (UTX) -> host direction (DTX), the data sent by our processor is received in TUSB1044A and is amplified/attenuated by EQ-gain values, set by pins UEQ[1:0], and then sent out towards host by using DC-Gain/VOD values, set with CFG[1:0] pins?

Likewise the data sent by Host-PC (DRX -> URX), is received in re-driver with amplification set by DEQ[1:] and sent towards device processor with DC_Gain / VOD settings selected with CFG[1:0]?

If SWAP = ”L” = ”0” = 1kΩ to GND, In Table 7-9 ”downstream” means data from re-drived towards our device’s processor and similarly the ”upstream” the direction from re-driver towards host-pc?

an example:

Since in our device, the Type-C connector is on FPC, a ~4 inches away from the (device) processor, we need slightly more amplification. From Type-C connector torwards Host-PC we are using AoC (active optical cable), which does not attenuate the USB3 signal considerably, so boostin isn’t required that much on that direction:

UEQ1 = R (20kΩ to GND)
UEQ0 = R

Re-Driver amplifies the signal coming from our device-processor by 3.0/3.5dB

DEQ1 = 0

DEQ0 = F

Re-Driver amplifies the signal coming from host via AoC-cable by 0/0.4dB

CFG1 = R
CFG0 = R
Re-Driver boosts the data sent towards our processor by 1dB, but the amplification towards Type-C connector / AoC-cable / host is 0dB. The linear region for both directions is 1100mV

Hopefully you are able tell us whether we have understood correctly the configuration of this chip, and if not, kindly requestng to tell where it went wrong.