Interface forum - Recent Threads

DS90LT012AH: THERMAL DATA FOR DS90PB975-Q1

Zack Herchen — Wed, 26 Aug 2026 18:22:27 GMT

Part Number: DS90LT012AH
Other Parts Discussed in Thread: DS90PB975-Q1

** TI part number in ticket is not correct because the P/N I'm looking for, DS90PB975-Q1, is not listed

Do you have thermal information for this component? Specifically I'm looking for the following:

Theta JB
Theta JC
Maximum Tj or Tc

Thanks,

Zack

DS90UB948-Q1: how to drive three display with one Des

Bingyun Yang — Wed, 26 Aug 2026 15:38:54 GMT

Part Number: DS90UB948-Q1

Hi team,

Our customer is designing a display box with 3 displays with exactly the same specifications(720 * 720, 60 FPS, 24 bits, MIPI interface).I know that using two Des in cascade can drive 4 screens. But two deserializers are a bit expensive. Is there a way to use one deserializer to output three displays? The deserializer model can be adjusted, doesn't have to be 948.

Could you please help to give some advice? Thanks!

Best Regards,
Bryn Yang

DP83822I: Implementation Guidance and Register Definitions for Active Link Cable Diagnostic (ALCD)

Wayne Tam — Wed, 26 Aug 2026 15:31:34 GMT

Part Number: DP83822I

Hi,

Our company is using the DP83822I PHY in a production design, and we want to implement the Active Link Cable Diagnostic (ALCD) feature to assess cable length and link quality.

While the feature is referenced in Registers 0x0155 (Table 8-50), 0x0215 (Table 8-66), and 0x021D (Table 8-67) of the datasheet (https://www.ti.com/lit/ds/symlink/dp83822i.pdf?ts=1787638832460&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FDP83822I), there is no detailed documentation explaining the implementation workflow or how to interpret the results.

Specifically, we need guidance on the following:

Test Execution Workflow: What is the correct sequence of register writes required to trigger and execute an ALCD test?
ALCD Sum Out Interpretation: What does the raw data in the ALCD sum out registers actually represent (e.g., specific distance metrics, SNR, or an internal error counter)? How do we convert these register values into physical distance (meters) or a concrete quality metric?
Application Notes: Is there an unlisted application note or reference code available for the DP83822 family that covers ALCD or generic Cable Diagnostics (TDR)?

Any code snippets, flowcharts, or register-level documentation you can provide would be greatly appreciated.

Thanks,
Wayne

TUSB212: EQ Setting

GARETH OU — Wed, 26 Aug 2026 15:20:35 GMT

Part Number: TUSB212

R272 and R273 are currently set to NC.

Regarding R274, it is currently set to 3K. Could you please advise whether this value is appropriate, or if it should be reduced further?

The customer's application is a 5-meter Type-C cable, and the signal includes USB 2.0. If you have any recommended EQ settings for this application, please kindly let us know as well. Thank you!

AM26C31: AM26C31 pins 13 and 14 output polarity reverses again after IC replacement

THANGAMUTHU N — Wed, 26 Aug 2026 14:08:48 GMT

Part Number: AM26C31

Hello TI Team,

I am facing an unusual issue with the AM26C31 differential line driver on one of our MCU boards.

At one particular channel, the differential outputs at pin 13 and pin 14 are observed with reversed polarity compared with the working MCU board.

The MCU input signals to the AM26C31 are correct. We verified the signals by comparing them with a working MCU board.

When we replace the AM26C31 IC with a new IC, the outputs at pins 13 and 14 become normal. However, after some time of operation, the same output polarity reversal occurs again on the same PCB.

Since replacing the IC temporarily resolves the issue, but the same behaviour returns on the same PCB.
Under which operating conditions can the AM26C31 output polarity between pins 13 and 14 become reversed?

AM3352: Query Regarding the BOOT MODE SEQUENCE AND GPMC

Krishan Arora — Wed, 26 Aug 2026 13:50:21 GMT

Part Number: AM3352

Hello Team,

We have a few questions regarding the BOOT mode sequence and the fallback behavior of the boot ROM.

We are using the GPMC interface with an 8-bit NAND, and in one of the boot mode configurations, we are planning to use NAND as the primary boot source and MMC0 (SD card) as the secondary boot source:

NAND → NANDI2C → MMC0 → UART0

Our primary boot interface in this configuration is NAND, with MMC0 as the fallback boot source.

We have the following concerns:

1. MMC1 → MMC0 Boot Sequence

We are not using MMC1 as our primary booting interface. Our primary boot interface is MMC0 (SD card).

For the following boot sequence:

MMC1 → MMC0 → UART0 → USB0

the boot ROM will first attempt to boot from the MMC1 peripheral at Stage 1. Since we do not have any MMC1 device connected, our concern is:

If the boot ROM encounters an error while trying to access MMC1, will it automatically recover/timeout and proceed to MMC0?
Is there any possibility that the boot process could get stuck at the MMC1 stage and never reach MMC0?

2. NAND → NANDI2C → MMC0 → UART0 Boot Sequence

We are also using GPMC with an 8-bit NAND, and for the following boot sequence:

NAND → NANDI2C → MMC0 → UART0

NAND is our primary boot source and MMC0 is the secondary/fallback boot source.

If the NAND is blank/not populated during the first boot, i.e., there is no valid boot code available in NAND, will the boot ROM automatically detect the failure and proceed to the next boot source, NANDI2C and then MMC0?

We would like to understand whether the same fallback behavior applies here as in the MMC1 → MMC0 case, or whether a blank/unprogrammed NAND can cause the boot process to get stuck.

3. NANDI2C / I2C0 Configuration

For the NANDI2C boot stage, we have not connected any EEPROM or other boot device on I2C0. The only device connected to I2C0 is the PMIC.

Could you please confirm whether the absence of an EEPROM/boot device on I2C0 can cause any issue during the NANDI2C boot stage, or whether the boot ROM will simply fail that boot attempt and proceed to MMC0?

Overall, since MMC0 (SD card) is our available fallback boot source, we want to ensure that the boot ROM will reliably move to MMC0 whenever the preceding boot source is unavailable, blank, or fails to provide valid boot code.

Please advise on the recommended boot mode configuration and the expected fallback behavior in these scenarios.

QUE2: I want to use GPMC in which i want to connect NOR FLASH, what is the Maximum size of NOR flash i can use?

TUSB422: Need support for TUSB422 software support...

Peter Tseng — Wed, 26 Aug 2026 13:47:11 GMT

Part Number: TUSB422

Hi Team,

Please help to support TUSB422 Linux driver for Android16 (linux kernel-6.1) and driver porting guide document.

Thanks.

DS90UB948-Q1: Compatibility with DS90UB927-Q1 serialiser

sevender sharma — Wed, 26 Aug 2026 13:37:35 GMT

Part Number: DS90UB948-Q1

Hi Ti team,

Please confirm the compatibilty of DS90UB948-Q1 deserialiser with DS90UB927-Q1 serialiser. Can I use in these two in conjunction.

THVD4411: Mode Selection Details for MODE1/MODE0 = 00 (L-L) State

Ajmal A — Wed, 26 Aug 2026 10:24:21 GMT

Part Number: THVD4411

Dear TI Support Team,

I am reviewing the datasheet for the THVD4411, specifically Section 7.4.3, Table 7-8: MODE Control Function Table.

The table defines the following operating modes:

However, the combination of MODE1 = L and MODE0 = L (both Low) is not listed in the table.

Could you please clarify:
1. What is the defined operating mode or function when both MODE1 and MODE0 are set to Low (L-L)?
2. Is this state reserved, undefined, or does it invoke a specific function such as a loopback, shutdown, or test mode?
3. If it is reserved, should this state be avoided during normal operation, and are there any precautions needed to prevent accidental entry into this state?

For context, I am designing a system that may have both pins pulled Low during power-up transients, so understanding the behavior in this state is critical for my application.

Thank you for your assistance.

Best regards,
Ajmal Aboobakar

DP83867IR: Multiple PHYs on one MDIO Interface

phytecBSC — Wed, 26 Aug 2026 09:50:59 GMT

Part Number: DP83867IR
Other Parts Discussed in Thread: AM62L

Hello everyone.

Currently I have a system which uses the AM62L and has only one MDIO interface.
We have one Ethernet PHY on the SOM and another one on the CB (carrierboard).

Now I see an issue, that when the CB PHY is connected, the CB PHY refuses to answer.

Here is the scenario where only PHY0 is attached

Here is the scenario where only PHY1 is attached

In about 1 of 100 cases both work fine, but overall it behaves as above where only one is seen.

I also tried to set the SOM PHY to address 2, but it behaves exactly the same.

Do you have an idea what could be wrong here? Or what I can test?

Cheers

TCAN1473-Q1: WAKE pin routing if unused (TCAN1473-Q1)

Chase Jeong — Wed, 26 Aug 2026 09:37:55 GMT

Part Number: TCAN1473-Q1

Dear TI experts,

Could you check that how can I route WAKE pin if I do not use it?

Datashet says that it should be pulled to Vsup or ground, it is not clear.

What is your best choice?

Connect to Vsup directly
Connect to Vsup using pull-up
Connect to GND directly
Connect to GND using pull-down

Best regards,

Chase

TCAN1145-Q1: Unintended flag asserted

Yuya Shoji — Wed, 26 Aug 2026 08:42:12 GMT

Part Number: TCAN1145-Q1

Hi team,

I'm BCCing my customer.

They observed that FSM_CONFIG[3:1] is set as 010b which is reserved settings. They found it with following handling.

a. Read FSM_CONFIG=>0x00h

b. Power down ECU with following order

VIO->VCC->VSUP

c. Power up ECU(at this moment, VSUP is around 4V due to residual voltage)

d. Read FSM_CONFIG=>0x04h

Q1. What condition can cause this register setting?

Q2. Is FS_STAT=010b okay to operate the device?

Q3. If Q2 answer is NO, how should user manage this?

Best Regards,

Shoji

TCAN1145-Q1: Thermal resistance availability for D pkg

Yuya Shoji — Wed, 26 Aug 2026 08:26:14 GMT

Part Number: TCAN1145-Q1

Hi team,

I'm BCCing my customer.

Do you have R_thetaJC(bot) for D pkg?

Best Regards,

Shoji

DS160PR410: What is the physical meaning of DC gain variation and EQ boost varation?

Lawrence He — Wed, 26 Aug 2026 08:20:10 GMT

Part Number: DS160PR410

Hi, Support Team

we have a few technical questions regarding the DCGAINVAR and EQGAINVAR specifications in the datasheet:

What is the physical meaning of DC gain variation and EQ boost varation?

Impact of Variations on Channel Loss Budget?
Mitigation & Tuning Recommendations?

if any, Please advise me.

Thanks,

Best regards,

Lawrence

THVD8000: THVD8000 Immunity problem

Malo Hénaff — Wed, 26 Aug 2026 08:19:53 GMT

Part Number: THVD8000

Hello,

We have a problem during EMC test : Conducted radio frequency (IEC 61000-4-6). The severity of the test are :

Frequency range: 150 kHz – 80 MHz
Amplitude: 3 V r.m.s. h
Modulation***: 80 % AM at 1 000 Hz
Frequency sweep range:
≤ 1,5 × 10–3decades/s (or 1 %/3 sec.)

After that, the test levels shall be increased to 10 V r.m.s. for spot frequencies in accordance with IEC 60945 at 2 ; 3 ; 4 ; 6,2 ; 8,2 ; 12,6 ; 16,5 ; 18,8 ; 22 ; 25 MHz.

We are using a THVD8000 with a 1 MHz carrier and a baud rate of 115200 BAUDS. The schematic is has below

We have replace C520 and C521 by 100pF value and we have replace the R512 resistor by two 60 resistors with 220pF capacity between the two resistor and 0V. We have replace the self by 744227 (mor efficient as 744252220)

Our electronic is connected on the another electronic with the same schematic. the cable is shielded and the cable shield is connected to the guard ring on our board.

When the perturbation is launched (especially during the spots with 10 V r.m.s) we have some communication FAULT with the THVD8000. We can observe that, the LED 501 stay light during all the perturbation.

But if the shield câble is not connect on our ring no problem appears => So we suppose the HF pertubation pass by the ring and small capacity (47pF) place between the ring and our 0V and the noise pass in the THVD by 0V.

Did you have some recommandation about that ? Place ferrite between 0V and 0V pin of the THVD8000 ? Do not connect the shield on the ring ?

Best Regards

Malo

PCA9548A: back-powering via PullUp PCA9548A

Timo Reinhardt — Wed, 26 Aug 2026 07:10:41 GMT

Part Number: PCA9548A
Other Parts Discussed in Thread: TCA9548A

Hi,

I got a test setup which utilize a PCA9548A to control 8x DUT (on a test socket). The supply for DUT (VCC) is switchable.
Once I tun off VCC and unselect all channel, I still got a small voltage coming via the PullUps, as PCA9548A (in my understanding) is pulling those lines up in idle/unselect situation. This is preventing my DUT so safely beeing unpowered.

Question: is there a chance to unselect all channels and keep the outputs to Low, so as a result VCC will be 0V as well?

DP83867CS: XI-XO application

Koshi Ninomiya — Wed, 26 Aug 2026 06:53:38 GMT

Part Number: DP83867CS

Dear Team,

My customer is designing the DP83867CS application circuit, and has some questions as follows,

Q1: XI-XO application
My customer uses a crystal between XI-XO.
Datasheet shows the crystal oscillator circuit. There is not a 1Mohm between XI and XO.

However, DP83867EVM has a 1Mohm between XI and XO.

When do they need this 1Mohm between XI and XO ?

Q2: Unused pins
What is the proper way to handle unused pins?
What is the internal pull-up/down resistor value?

Q3: INT pull-up resistor value
What is the proper resistor value of INT pull-up?
Is 10kohm pull-up resistor OK?

Best Regards,

Koshi Ninomiya

DS80PCI402: SCH review

Leo Chung — Wed, 26 Aug 2026 06:41:44 GMT

Part Number: DS80PCI402

please help review DS80PCI402SQ/NOPB SCH design

replay_8port_ext_v1_sch_20260826.pdf

AM62A7-Q1: EMMC bare chip programming , AM62A7 initialization failed

liu xiwen — Wed, 26 Aug 2026 06:15:50 GMT

Part Number: AM62A7-Q1
Other Parts Discussed in Thread: AM62A7

Hi,team

Our project uses the AM62A7 platform. During the software debugging process, we encountered the following issues. The EMMC chip downloads the software through the bare chip software burning method. After the software is burned onto the EMMC chip and then attached to the PCBA and powered on, we found that the system's power could be turned on, and the PMIC also powered on the power supply for the AM62A7. However, the AM62A7's UART serial port did not print any logs, and the software did not run successfully. It seemed that the startup process got stuck at an unknown position. After the ECU was powered on and off again, the AM62A7 system could start and run normally. This issue was 100% reproducible. We would like to ask if your team has encountered this problem before and if you could provide some solutions. Thank you.

Thanks,

Xiwen

TLIN1021A-Q1: Duty cycle patterns and related timing parameters

Masaru Oinaga — Wed, 26 Aug 2026 03:25:31 GMT

Part Number: TLIN1021A-Q1

Hello, Team,

We would like to understand the timing parameters given in the datasheet, especially ones related to duty cycle D1 ~ D4. We are a bit confused with what are the relationship between these parameters and how we should use them when designing a system.

Below is the combined image of Figure 8-9 and 8-11.

Main questions are:

What is the relationship between Td-r max and trx_pdf(1), Tr-d max and trx_pdr(2)?
- Does Td-r max (Tr-d max ) include trx_pdf(1) (trx_pdr(2))?
Based on Figure 8-11 and T_{d-r max} spec in the Electrical Characteristics, it appears there is a discrepancy in the definitions: TH_REC(MIN), rather than TH_REC(MAX), is equal to 0.422 x V_SUP, and TH_DOM(MIN), rather than TH_DOM(MAX), is equal to 0.284 x V_SUP. Could you please clarify if this is an error in the text?

Best,
Masaru

TLIN1028-Q1: Question about thermal characteristics (TLIN10283DRBRQ1)

Chase Jeong — Wed, 26 Aug 2026 00:52:23 GMT

Part Number: TLIN1028-Q1

Dear TI experts,

My customer now test TLIN10283DRBRQ1 in their own PCB.

Input is 12V car battery, and output is 3.3V / less than 10mA.

the temperature rises about 3℃ compared to ambient temperature. This is not a big deal but the application is humidity sensor, so it has more error rate.

As you know the device includes LDO, so I know that it should have rising temperature. Just I want to know if there is any ways to lower temperature rising.

Best regards,

Chase

DP83867E: MDI interface speed automatically follow the speed of the 88Q2112?

Danilo A. — Tue, 25 Aug 2026 21:39:52 GMT

Part Number: DP83867E

Hi Team,

Posting on behalf of our customer.

I am using the 88Q2112 and DP83867 with an SGMII interface to implement a media converter function that converts automotive Ethernet to standard Ethernet. The 88Q2112 is manually configured with a fixed speed and master/slave mode, while the DP83867 has SGMII enabled and MDI auto-negotiation enabled.

When switching the speed of the automotive Ethernet link, the PC Ethernet adapter must be manually configured to 100 Mbps or 1000 Mbps in order to establish communication.

Is it possible to make the DP83867 MDI interface speed automatically follow the speed of the 88Q2112?

Regards,

Danilo

GD75232: GD75232 power sequencing

B. Hussain — Tue, 25 Aug 2026 19:17:11 GMT

Part Number: GD75232
Other Parts Discussed in Thread: GD65232, TRS3243E, TMUX7462F

I note that the datasheet for GD75232 says in section 5.2 Recommended Operating Conditions, Note 1:

When powering up the GD65232 and GD75232, the following sequence should be used:
VSS, VDD, VCC, I/Os
Applying VCC before VDD may allow large currents to flow, causing damage to the device. When powering down the GD65232 and GD75232, the reverse sequence should be used

Could some elaboration be provided on the potential issues caused, and the reason why?

In my design I may have an infrequent usage scenario where the GD75232 is powered by VCC (with +5V) when VDD and VSS supplies are not present. The scenario is when a firmware update is being performed on an embedded microcontroller, where +5V is being supplied to VCC by USB, but the regular PSU is not connected and thus not delivering +12V and -12V to VDD and VSS (that is, they will be floating, not at 0V).

I also do not see any such note or caution in the datasheets of other pin-compatible 75232 devices from other manufacturers, so I am wondering if this issue is specific to TI, or these other manufacturers simply do not mention it.

If such a scenario is definitely not recommended, can any suggestions be made as to how I can gate VCC to the GD75232 in the presence/absence of VDD and VSS?

SN65LBC179: obsolescence report for the components

Hardware Intern — Tue, 25 Aug 2026 12:11:30 GMT

Part Number: SN65LBC179

Could you please provide an obsolescence report for the components listed below? We are seeking long-term availability for a minimum of 10 years. For our internal tracking, we categorize obsolescence into the following four groups:

- Category A: EOL > 10 years
- Category B: EOL > 5 years
- Category C: NFRD / Obsolete
- Category D: EOL not confirmed by manufacturer

Components:

SN65LBC179QDR

SN65DSI84: Mouser Tech Request - Q2679D6

Grzegorz Bartosz — Tue, 25 Aug 2026 10:14:40 GMT

Part Number: SN65DSI84

Hello,

I hope you are well,

Could you please advise if there is suitable alternative that is usable for RGB + Sunc to PAL composite Encoding that is similar to ADI AD725ARZ?

Thanks,