Interface forum - Recent Threads

DS90UB904Q-Q1: DS90UB904Q Receiver Staggered Output: Is it user-configurable

kunitaka nakagawa — Fri, 03 Apr 2026 05:59:46 GMT

Part Number: DS90UB904Q-Q1

Hello TI team,

We are using DS90UB903Q / DS90UB904Q in Display mode.

The datasheet mentions “DES Receiver Staggered Outputs” as an EMI reduction feature on DS90UB904Q,
but we could not determine from the public documentation whether this function is fixed or user-configurable.

Could you please clarify:
1. Is Receiver Staggered Output user-configurable (enable/disable)?
2. If yes, which register/bit controls it?
3. What is the default setting?
4. Can the amount of staggering (timing spread / stagger width) also be configured?
5. Is this feature active in Display mode?

BIST mode is not used in our application.

Thank you.

RE: DS90UB904Q-Q1: DS90UB904Q Receiver Staggered Output: Is it user-configurable

Hamzeh Jaradat — Sat, 04 Apr 2026 01:07:04 GMT

Thank you for your message. Our team is currently out of office due to the holiday period. We will respond to your request when we return on Monday, April 6, 2026. Thank you for your understanding.

DS90UB947-Q1: When powered on, there may be screen flickering and black screen phenomenon

Jon WANG — Thu, 02 Apr 2026 15:14:52 GMT

Part Number: DS90UB947-Q1

When powered on, there may be screen flickering and black screen phenomenon. Please refer to the attachment for details.
The following is the troubleshooting process:
1. When the screen is blurred, we performed ABA swapping on the display screen where the 948 chip is located, and found that the blurred phenomenon always follows the host where the 947 chip is located
2. Now it is confirmed that resetting DS90UB947TRGCRQ1 alone can restore it, indicating that DS90UB947TRGCRQ1 is working abnormally internally
At present, there is a delay of 200ms in PDB time, which can reduce the probability of screen burn-in. However, there are still about 1/600 instances that cannot be resolved.

The main difficulty lies in how customers can determine whether the OLDI data has normal values

yaxon DS90UB947TRGCRQ1 issue.xlsx

RE: DS90UB947-Q1: When powered on, there may be screen flickering and black screen phenomenon

Hamzeh Jaradat — Sat, 04 Apr 2026 01:05:30 GMT

Thank you for your message. Our team is currently out of office due to the holiday period. We will respond to your request when we return on Monday, April 6, 2026. Thank you for your understanding.

RE: DS90UB948-Q1: I would like to ask if there is a way to read the remote GPIO status of the DS90UB948-Q1.

Hamzeh Jaradat — Sat, 04 Apr 2026 01:01:10 GMT

Thank you for your message. Our team is currently out of office due to the holiday period. We will respond to your request when we return on Monday, April 6, 2026. Thank you for your understanding.

DS90UB948-Q1: I would like to ask if there is a way to read the remote GPIO status of the DS90UB948-Q1.

KISUK LEE — Fri, 13 Mar 2026 01:35:32 GMT

Part Number: DS90UB948-Q1

Dear TI SerDes FAE

This is an inquiry about a different project from the ongoing inquiry regarding DS90UB941AS-Q1.

When the DS90UB941AS-Q1 Serializer and DS90UB948-Q1 DeSerializer are linked, is there a way for the Host CPU to know the status of the GPIO output value of the DS90UB948-Q1 through the I2C of the DS90UB941AS-Q1?

The example of the connection structure between SerDes is similar to what was mentioned in another question.

[DS90UB948] I want to check specific GPIO settings via I2C in the Deserializer.

I simply thought that I could check the output value of GPIO3 by reading the [0x1F] Register.
I checked, and the output always reads 0x05. After reviewing the datasheet, I found that this can only be checked when Local GPIO is enabled, as shown in [Table 5] below.

We want to use Remote GPIO Enable, so the above method doesn't seem to work.

Is there a way to check the GPIO output value while Remote GPIO Enable is enabled?

I am contacting you because I could not find a solution, so please check into this.

SN75DP130: OrCAD Data Not Found

Masayuki Kai — Fri, 03 Apr 2026 18:00:39 GMT

Part Number: SN75DP130

Could you please share the OrCAD reference schematic and PCB data for the DP130SSEVM?

TUSB1210: Regarding the issue where the TUSB1210 fails to recognize a USB flash drive.

Boris liu — Thu, 26 Mar 2026 10:10:35 GMT

Part Number: TUSB1210

Hi Team,

We are currently planning to use the TUSB1210 to replace the USB3320C_EZK. The platform uses Intel’s Cyclone V SoC FPGA, and this platform works normally when driving the USB3320C_EZK.

At present, after the TUSB1210 is initialized, the CPEN pin is not enabled, so the USB connector does not output 5V. As a result, a USB flash drive cannot be recognized when inserted. The CLOCK signal on pin 26 is outputting a 60 MHz clock. I personally believe the issue is related to the PHY initialization.

Please help analyze the cause of the failure. Thank you.

RE: TUSB1210: Regarding the issue where the TUSB1210 fails to recognize a USB flash drive.

Brian Zhou — Fri, 03 Apr 2026 14:59:54 GMT

how is power on sequence? 3.3v should be applied before 1.8V.

regards

brian

RE: TUSB319-Q1: Does TUS319-Q1 support USB3.0

Brian Zhou — Fri, 03 Apr 2026 14:12:22 GMT

Hi Andy:

1.5A and 3A is type-C current mode, it's nothing to do with USb2 or USB3 application.

only difference is that in default current mode. For USb2, it's 500ma, 900ma for USB3.

Best

Brian

TUSB319-Q1: Does TUS319-Q1 support USB3.0

Andy Jin — Fri, 03 Apr 2026 09:30:41 GMT

Part Number: TUSB319-Q1

Hi Expert,

Please help confirm if TUSB319-Q1 suport to USB3.0 under Current Model=M/H.

Thanks a lot!

Andy

DP83848I: DP83848I SNI mode – RX_DV behavior and 10BT_SCR (Reg 0x1A) readback

Ryu Yamashita — Thu, 02 Apr 2026 00:56:02 GMT

Part Number: DP83848I

Hi team,

Background: We are using DP83848IVV/NOPB in SNI mode (10 Mbps). Hardware strap settings per datasheet have been applied and reset is released correctly. However, we observe RX_DV (pin 39, RX_DV/MII_MODE) asserting during packet reception, even though the datasheet states “This pin is not used in SNI mode.” Additionally, when we read Register 26 (0x1A, 10Base‑T Status/Control, 10BT_SCR), we get 0x0001, while we expected 0x8000 as an indicator of SNI mode.

Questions:

In SNI mode, is RX_DV guaranteed to be static (low/high) or high‑impedance, or can it still toggle/reflect internal receive‑valid activity even though it is “not used”? Please clarify the intended/guaranteed behavior for pin 39 in SNI.
For 10BT_SCR (Reg 0x1A): what is the correct bit definition for bit[15] (0x8000), and under what conditions should it read as 1? Is 0x8000 a valid “SNI mode” confirmation check?
Is any MDIO register write required to enter/lock SNI mode beyond reset strap configuration (e.g., forcing 10 Mbps, disabling auto‑negotiation), and do you recommend a specific register readback to confirm SNI operation?

Best Regards,
Ryu.

RE: DP83848I: DP83848I SNI mode – RX_DV behavior and 10BT_SCR (Reg 0x1A) readback

Fri, 03 Apr 2026 14:02:04 GMT

Hi Yamashita-san,

I agree with your opinion. It seems like the figure in the datasheet is wrong. Please check out Figure 4-15 of DP83848-EP datasheet for the correct figure.

https://www.ti.com/lit/ds/symlink/dp83848-ep.pdf

Best,

RE: AM26LV31: External Attribute Collection - Requesting MSL

Michael Ikwuyum — Fri, 03 Apr 2026 13:51:47 GMT

Hi Janani,

Today is a public holiday. Please help give until next week for feedback, thanks.

Best Regards,

Michael.

AM26LV31: External Attribute Collection - Requesting MSL

Janani Priya — Fri, 03 Apr 2026 02:59:33 GMT

Part Number: AM26LV31

Hello Respected,

This is Janani Priya , currently We are working for one of our Manufacturing plant, expecting your support to provide MSL Value for Below Provided MPNs

Your Quick action will be appreciated, In case if you are not the correct person, Please help us to redirect it to right contact

AM26LV31CDR

SN65HVD33-EP: Trying to figure out a failure that occurred with SN65HVD33MDREP

Nathan Wolfe — Thu, 26 Mar 2026 18:35:11 GMT

Part Number: SN65HVD33-EP

We use this chip in a test system that was connected to a DUT that was undergoing EMI/EMR testing. Referencing the picture, the test setup that should be understood is that the DUT was only connected to this chip via the RX_H and RX_L lines, but the tester does provide power to the DUT via separate lines in the same cable bundle. The 3.3V power to the chip is not in that cable and does not connect to the DUT. The physical cable is about 12 feet (3.7m) long. This is an unshielded cable which was mistakenly subjected to a CS116 test. However, our RS-422 lines are properly run as twisted pairs, and in addition they have TVS diode protection.

The test team observed after this test that the communication with the DUT failed, and upon observation of the chip itself we noticed that some melting had taken place. It was not an open crater, just an ellipsoid in the center of the chip that looked partially melted. We did not observe any visible damage on any pins. Unfortunately I cannot provide the chip or pictures of it. I would like to figure out the mechanism of failure so that the chip can be better protected in the future.

RE: SN65HVD33-EP: Trying to figure out a failure that occurred with SN65HVD33MDREP

Michael Ikwuyum — Fri, 03 Apr 2026 13:50:51 GMT

Hi Nathan,

Today is a public holiday. Please help give until next week for feedback, thanks.

Best Regards,

Michael.

TMDS1204: HDMI 2.1 4th data lane ibert error

Irfan Shaikh — Fri, 03 Apr 2026 13:32:48 GMT

Part Number: TMDS1204

Hi Team,

We are testing HDMI 2.1 and we did ibert test to check the data integrity.
I am facing issue in the 4th data lane, while i loop back from TX to RX, 4th data lane will show no link.

Suspecting that the retimer IC is not giving output on OUT_CLKn/p (39,40) as we have connected the output of IC from 39,40 th pin to the FPGA.

Since Mode pin is also PU(1k) so that there is no fan out buffer supported and all 4 data lanes should be output from the retimer IC.

So please let us know why no link is there on 4th lane.

Regards,
Irfan

LMH1208: Regarding the parameters of the LMH1297 IBIS-AMI model

Shingo Ozaki — Wed, 01 Apr 2026 08:49:05 GMT

Part Number: LMH1208

I am performing SI analysis on the LMH1208, and the IBIS-AMI model used is the LMH1297 model.


I have some questions regarding the Tx and Rx AMI parameters of the LMH1297.


1) The "EQ_Level" parameter in the Rx AMI model is described as setting the device register (Reg_0x03).

Does this refer to the "IN0 Manual EQ Boost" described in the "LMH1228, LMH1208 Programming Guide"?

If so, I believe there are 255 possible EQ Boost settings, but why can only values from 0 to 55 be set in the Rx AMI model?


2) Is the "DEM" parameter in the Tx AMI model only affecting the output waveform of the LMH1208's OUT0 terminal?

When adjusting the waveform of the SDI_OUT1+ terminal, should this parameter not be used for adjustment?

RE: LMH1208: Regarding the parameters of the LMH1297 IBIS-AMI model

Fri, 03 Apr 2026 13:27:27 GMT

Hi Ozaki-san,

I apologize for the inconvenience. I will get back to you on Monday.

Best,

TCA4311A: Hot-swappable I2C/SPI bus buffer with IRQ

Vincent Chiu — Wed, 01 Apr 2026 08:55:20 GMT

Part Number: TCA4311A

Hi TI expert

We have one hot swappable buufer for I2C with one interrupt (IRQ) and SPI with one interrupt (IRA), total is 8 pins.

For I2C, we have solution with TCA43111A, however, we need experts recommend for SPI and interrupt pins (IRQ)

Regards,

Vincent

RE: TCA4311A: Hot-swappable I2C/SPI bus buffer with IRQ

Jack Guan — Fri, 03 Apr 2026 13:22:29 GMT

Hi Vincent,

Today is a TI holiday, please allow some time for response.

Thanks,
Jack

RE: TCA9803: TCA9803

Jack Guan — Fri, 03 Apr 2026 13:20:03 GMT

Hi Silvas,

Today is a TI holiday, please allow some time for response.

Thanks,
Jack

TCA9803: TCA9803

Silvas Melshia — Fri, 03 Apr 2026 11:24:12 GMT

Part Number: TCA9803

Hi,

Can you please share the power dissipation value for this part

DP83869HM: Request for Schematic Review – Ethernet PHY (DP83869HMRGZR with AM2634)

Chinchetti Abhishek — Sat, 21 Mar 2026 05:45:43 GMT

Part Number: DP83869HM

Hello Team,

I am sharing our schematic here and would like to request your support for a detailed review.

We are working on a custom board where the DP83869HMRGZR Ethernet PHY is interfaced with the AM2634 MCU over RGMII. Currently, the Ethernet link is coming up (LED indication is present), but ping is not working.

I kindly request you to review the attached schematic and provide your feedback to help us identify the issue.

CUSTOM_BOARD-REV02.pdf

Please let me know if any additional information (such as oscilloscope captures or layout details) is required from our side.

Looking forward to your support.

--
Thanks & Regards,
Chinchetti Abhishek