Interface forum - Recent Threads

TCA4307: CS3533019: Information gathering for internal registration of "TCA4307DRGR"

Taishin Minami — Fri, 25 Sep 2026 00:41:20 GMT

Part Number: TCA4307

This is Minami from Mitsubishi Electric.

I previously contacted you regarding the case number referenced in the subject line. Thank you again for your support.

I apologize for the delay in getting back to you. Following our internal review, several additional questions and requests were raised regarding the component mentioned above.

Since the information we obtained from the website contained some inconsistencies and lacked certain details, I would greatly appreciate your assistance with the following inquiries.

Request

1. Completion and Return of Attached Documents

Could you please complete the attached documents and return them to us?

- confidential_r7104_y5.docx

- confidential_rs0270_y1_y2_e.xlsx

- confidential_rs1639_fz1-2.docx

- confidential_rs1639_fz1-4.docx

Note: "confidential_rs1639_fz1-2.docx" is for reference only and does not need to be returned.

2. Answers to the Following Questions

Could you please provide answers to the following questions?

We apologize if any of these questions overlap with items already covered in the documents above.

- What is the electrode plating thickness?

- Could you provide information regarding the allowable number of reflow cycles and the recommended reflow temperature profile?

- Is flow soldering permitted?

- Is manual soldering rework permitted?

In addition, if insufficient solder is detected, we may need to perform soldering iron rework (soldering iron tip temperature: approximately 350°C for about 3 seconds). Could you please confirm whether this procedure is acceptable?

- Is the electrode surface finish Sn (tin) plating?

- What is the component weight?

Requested Response Date

September 30

I sincerely apologize for requesting this additional information despite your busy schedule.

I would greatly appreciate it if you could review the above items and provide your guidance at your earliest convenience.

Thank you very much for your continued support.

Best regards,

DP83TC811-Q1: uest to Review DP83TC811-Q1 MII Back-to-Back Media Converter Application

Tan KC — Thu, 24 Sep 2026 23:39:58 GMT

Part Number: DP83TC811-Q1

Hi TI Support Team,

We are evaluating the DP83TC811-Q1 for a transparent 100BASE-TX to 100BASE-T1 media converter application without an MCU/MAC.

Our proposed architecture is:

100BASE-TX → KSZ8051MNL → MII → DP83TC811-Q1 → 100BASE-T1

The KSZ8051MNL will be configured in MII Back-to-Back mode, while the DP83TC811-Q1 will operate in MII mode. The attached block diagram shows our proposed connection.

Could you please review and confirm the following points?

Can the DP83TC811-Q1 MII interface operate directly with the KSZ8051MNL configured in MII Back-to-Back mode, without an intermediate MAC?
Is the following MII cross-connection valid?
- KSZ RXD[3:0] → DP83TC811 TX_D[3:0]
- KSZ RX_DV → DP83TC811 TX_EN
- KSZ RX_CLK → DP83TC811 TX_CLK
- DP83TC811 RX_D[3:0] → KSZ TXD[3:0]
- DP83TC811 RX_DV → KSZ TX_EN
- DP83TC811 RX_CLK → KSZ TX_CLK

Should RX_ER → TX_ER also be cross-connected in both directions for proper error propagation, or should TX_ER/RX_ER be left unused?
Can a common 25 MHz oscillator be used as the reference clock for both PHYs?
Can the DP83TC811-Q1 be configured completely using hardware bootstrap settings for this application, with no MDIO register writes or MCU required after power-up?
Are there any additional MII timing, clocking, reset, or bootstrap requirements that we should consider for this PHY-to-PHY application?

Our objective is a fully transparent and autonomous 100BASE-TX 4-wire to 100BASE-T1 2-wire converter.

It would be appreciated if a DP83TC811-Q1 applications engineer could review the attached architecture and advise whether this implementation is recommended.

Thank you.

Best regards,

KC Tan

DP83TC811_MCU_Free_100BASE-T1_Solution .pdf

ONET8501V: obsolete of ONET8501V

Amir Moses — Tue, 22 Sep 2026 10:47:41 GMT

Part Number: ONET8501V

Hi,

i need FFF solution for ONET8501V,

1 year ago you suggest me to take this compomemt and its obsolete.

who is the contact person in Israel please?

RE: ONET8501V: obsolete of ONET8501V

Drew Miller1 — Thu, 24 Sep 2026 22:30:31 GMT

Hi Amir,

I'm working to connect you with Israel support team. In parallel, you could reach out through https://www.ti.com/support/customer-support-center.html.

You would implement an attenuation network with the same topology shown in SLLA311. Although this is shown in the context of impedance matching, the same circuit can be used to attenuate the modulation current to the VCSEL.

Thanks,

Drew

LMH1219: Register flips causing video dropout

Dajon McGill — Thu, 17 Sep 2026 19:02:06 GMT

Part Number: LMH1219

We're using the LMH1219 low power 12G UHD adaptive cable equalizer with integrated reclocker in our video equipment, running both 3G-SDI and 12G-SDI signals.

We're seeing video drop out over time, and on loss and reconnection of video. When this happens, Register 0x7 on the CableEQ/DivEQ page changes from 0x24 to 0xFF. This is the specific register change that correlates with video stopping. We're also seeing other registers change unexpectedly, but 0x7 is the one that breaks video.

This is occurring on some units but not others, all from the same manufacturing batch.

Can you tell us what Register 0x7 controls and what conditions would cause it to transition from 0x24 to 0xFF?

RE: LMH1219: Register flips causing video dropout

Dajon McGill — Thu, 24 Sep 2026 21:00:35 GMT

[quote userid="567304" url="~/support/interface-group/interface/f/interface-forum/1683332/lmh1219-register-flips-causing-video-dropout/6491666"]Are we certain the customer is not writing 0xFF to this register when the issue happens? From what I can gather, the device should not be changing the value in this register by itself.[/quote]

[Alex] That’s good to know. When this occurs, software should only be reading status – not performing any config. That said, our interim field solution is to disable all device access following initialization, in which case the video dropout issue has not been observed. So, we’re open to the idea that an intended read may, somehow, become a write. Albeit, so far, we haven’t managed to capture an SPI transaction that looks like a write on oscilloscope. Below are measurements of timing parameters, with the one marked in red now addressed in software that’s pending test (doesn’t seem likely to be the issue). Looking at how the software person implemented the protocol, I’ll likely seek clarification on a couple of things that the datasheet doesn’t confirm for me, but I’m currently awaiting another unit for further probing, and to capture waveforms for context. I should note that SPI devices are daisy-chained four-deep, with the first two devices being LMH1219 and the other two being LMH1218. The issue has, so far, only been observed for the second LMH1219 device in the chain.

Parameter	Spec	Measured
FSCK	20MHz max	~32KHz
TSCK	50ns min	~27us
TPH	0.4xTSCK min	~4us at first cycle of each burst, ~12us for subsequent
TPL	0.4xTSCK min	~13us
TSU	4ns min	~10us for MOSI, ~13us for Dev1->2
TH	4ns min	~7.4us for MOSI, ~4us for Dev1->2
TSSSU	14ns min	~34us
TSSH	4ns min	~43us
TSSOF	1us min	~27us
TODZ	20ns typ	~0us
TOZD	10ns typ	~0us
TODZ	15ns typ	~0us

[quote userid="567304" url="~/support/interface-group/interface/f/interface-forum/1683332/lmh1219-register-flips-causing-video-dropout/6491666"]The fact that this is only seen on certain devices is strange as well. If the customer performs an ABA swap between a working board and failing board, does the failure follow the Device or the board?[/quote]

[Alex] We’re currently awaiting additional units from the field and could try this once we have enough.

[quote userid="567304" url="~/support/interface-group/interface/f/interface-forum/1683332/lmh1219-register-flips-causing-video-dropout/6491666"]By video drop out over time, do you mean the Video stops transmitting from the LMH1219 after a certain point? How long does it take before video drops out?[/quote]

[Alex] We’ve been replicating by interrupting video to the device repeatedly and it can take a few, to many interruptions. Temperature also seems to have some effect (which makes it seem like it could be a timing or amplitude margin issue, but amplitudes look good and timing is as given above). We can restore video by writing the register back to 0x24. It can also be replicated by writing the register to 0xFF followed by a video interruption.

TFP401A-EP: TFP401AMPZPEP plating process

Aaron Spaete — Thu, 24 Sep 2026 16:29:16 GMT

Part Number: TFP401A-EP

Team,

Minor question driven by a customer on TFP401AMPZPEP. The item has very low nickel content used on the lead frame plating, .94% total by weight but one question was how the plating is achieved on the lead frame.

Typically some type of electrodeposition is used, but perhaps electroless?

Regards,

Aaron

RE: TFP401A-EP: TFP401AMPZPEP plating process

David (ASIC) Liu — Thu, 24 Sep 2026 20:53:03 GMT

Aaron

This is done through electroplating.

Thanks

David

LMH1297: LMH1297 – Configuration and Lock Behavior with Two Devices in CD and EQ Modes

Abhinav Sundriyal — Thu, 24 Sep 2026 13:21:11 GMT

Part Number: LMH1297

Hello Team,

I am working with two LMH1297 devices connected in an SPI daisy-chain configuration for an SDI video application.

First, I have verified the SPI communication with both devices. I am able to read the Device ID from both LMH1297 ICs through the daisy-chain connection, so the SPI interface and daisy-chain communication appear to be working correctly.

My intended configuration is:

LMH1297 #1: CD (Cable Driver) mode
LMH1297 #2: EQ (Equalizer) mode

I am configuring both devices through the SPI interface and following the register sequences provided in the LMH1297 Programming Guide. I am referring specifically to Page 5, Section 3.1 "Common Device Configuration", including:

Section 3.1.1: EQ Mode for SDI_IO+ to OUT0± and SDI_OUT+ (All Retimed Data)
Section 3.1.2: CD Mode for IN0± to OUT0±, SDI_IO+, and SDI_OUT+ (All Retimed Data)

Currently, I send the complete register configuration sequence only once during initialization for both EQ and CD modes. However, my SDI video tests are not successful for either the SDI input/EQ path or the SDI output/CD path.

I would like to clarify the following points:

Does the LMH1297 can operate in either EQ mode or CD mode by default, depending on the default state of the EQ/CD SEL pin, or is it necessary to configure the relevant registers through SPI before the device can operate in either EQ or CD mode?
Should the configuration sequence be written only once or periodically? Once the complete CD/EQ register configuration sequence has been successfully written through SPI, should the sequence be sent only once during initialization, or is it expected that the register configuration needs to be repeated periodically? My current implementation sends the complete sequence once after power-up.
Should the ENABLE pin be toggled after SPI configuration? After completing the SPI register configuration, should I toggle the ENABLE pin or should it remain High throughout the configuration?
How should the two LMH1297 devices be configured through the SPI daisy chain? Since the two devices form a daisy chain, should each SPI transaction contain 34 bits (17 bits per IC), with the required command for one IC and dummy bits for the other? Or should both ICs be configured together in each 34-bit frame?
Does the Lock_N pin remains high until the Video gets locked?

Thank you for the support.

RE: LMH1297: LMH1297 – Configuration and Lock Behavior with Two Devices in CD and EQ Modes

David (ASIC) Liu — Thu, 24 Sep 2026 20:52:05 GMT

Hi,

Please see my inserted response below.

Does the LMH1297 can operate in either EQ mode or CD mode by default, depending on the default state of the EQ/CD SEL pin, or is it necessary to configure the relevant registers through SPI before the device can operate in either EQ or CD mode?

If the LMH1297 must be programmed with settings other than what is offered by the ED/CD sel pin control, you then must use SPI or SMBus mode for additional programming.

Should the configuration sequence be written only once or periodically? Once the complete CD/EQ register configuration sequence has been successfully written through SPI, should the sequence be sent only once during initialization, or is it expected that the register configuration needs to be repeated periodically? My current implementation sends the complete sequence once after power-up.

The configuration sequence is written only once. You do not need to repeat periodically. The configuration sequence will only be cleared if your power down the LMH1297.

Should the ENABLE pin be toggled after SPI configuration? After completing the SPI register configuration, should I toggle the ENABLE pin or should it remain High throughout the configuration?

No, you do not need to toggle the ENABLE pin after the SPI configuration.

How should the two LMH1297 devices be configured through the SPI daisy chain? Since the two devices form a daisy chain, should each SPI transaction contain 34 bits (17 bits per IC), with the required command for one IC and dummy bits for the other? Or should both ICs be configured together in each 34-bit frame?

In a daisy-chain configuration of N × LMH1297 devices, the host conceptually sees a shift register of length 17 × N for a basic SPI transaction, during which SS_N is asserted low for 17 × N clock cycles. Please also see this E2E thread for additional detail on the SPI operation, https://e2e.ti.com/support/interface-group/interface/f/interface-forum/754120/lmh0397-lmh0397-12xx-ss_n-deassertion-timing-for-spi-read-operation?tisearch=e2e-sitesearch&keymatch=SS_N.

Does the Lock_N pin remains high until the Video gets locked?

By default, LOCK_N is the reclocker lock indicator, and this pin asserts low when the LMH1297 achieves lock to a valid SMPTE data rate.

Thanks

David

RE: TMS570LC4357-EP: Inquiry Regarding Safety Analysis, Failure Modes, and Lock-Step Architecture for Landing Gear Control Unit Application

Ryan Davitt — Thu, 24 Sep 2026 19:42:08 GMT

Hey Yiğitcan,

Apologies for the delay. I have been looking for apps notes and other collateral that may be useful to you here. However, I have had no such luck in finding any existing information to "convert" from our usual IEC61508 and ISO26262 FMEDA to the SAE ARP4761 guidelines you are adhering to.

I am going to continue to push this request for ARP4761 relevant FMEDA-related information to the rest of our team for functional safety, and I will follow up with any information that comes out of that. However, at this time, we have no documents that may be applicable for you.

If you have any questions in relation to specific IEC61508/ISO26262 terminology or datapoints to help you apply it to ARP4761, please feel free to follow up.

Best,

Ryan

TMS570LC4357-EP: Inquiry Regarding Safety Analysis, Failure Modes, and Lock-Step Architecture for Landing Gear Control Unit Application

Yiğitcan Genç — Tue, 08 Sep 2026 05:28:16 GMT

Part Number: TMS570LC4357-EP

Dear Support Team,

We are currently evaluating your microcontroller for use in a safety-critical Landing Gear Control Unit (LGCU) project. While we have successfully utilized this device in previous non-safety-critical designs, this application requires a formal safety and reliability analysis. We have already opened a case with TI Support to obtain the necessary safety documentation.

Ahead of finalizing our Non-Disclosure Agreement (NDA) and receiving the detailed safety package, we would appreciate preliminary technical guidance regarding potential single-point and common-mode failure conditions.

To give you context on our system architecture:

Critical Hazard: Our primary concern is preventing an "Uncommanded Extension of the Landing Gears," which is classified as a catastrophic hazard.
Control Architecture: The microcontroller controls both the main pressure line and the gear pressure line via Solenoid Operated Valves (SOVs).
Fault Tree Analysis: Our preliminary analysis indicates that two independent failures are required to reach the top event, meaning it is not a single-point failure. However, because the microcontroller acts as a shared element, we are seeking safety analysis data that demonstrates how the device's lock-step architecture effectively mitigates potential common-mode or systematic failures.
Functional Availability: Additionally, we must ensure that a complete loss of microcontroller functionality is properly accounted for, as it manages critical control logic.

Could you provide a high-level heads-up or preliminary confirmation on whether these specific failure conditions involve any single points of failure while we await the formal NDA and detailed safety reports?

Thank you for your assistance and support.

DP83826I: DP83826I Analog Portion Failure After ESD Event

Jan D — Thu, 24 Sep 2026 10:21:22 GMT

Part Number: DP83826I

Hi Team,

We are facing an issue with our design using the DP83826I. After an ESD event, the analog (bias) portion of the PHY appears to fail, while the digital functionality remains operational. The issue occurs sporadically during production and affects a small percentage of the devices.

During our investigation of this failure, we were able to reproduce the same issue by applying a 1 kV, 10/100 µs surge to the Ethernet pairs. In this case, the analog (bias) portion of the PHY was damaged, while the digital portion of the DP83826I remained fully functional. The RMII, management interface, and clock output continued to operate without any issues. We found that the surge caused damage only when the device was powered. When the device was unpowered, it survived the same surge without any damage.

The main symptom of the damaged device is incorrect bias on the TX lines. The damaged PHY is unable to establish communication with 100 Mbps switches, while communication with 10 Mbps switches still works. We also found an abnormal voltage on pin 2 (CEXT) of the damaged devices. On a properly functioning device, the CEXT voltage is approximately 1.7 V. However, the damaged devices show different voltage levels and behaviors on the CEXT pin. Some devices randomly alternate between 0 V and 1.7 V, while others remain at 0 V or show approximately 2 V with small voltage spikes. This indicates that the damaged devices do not all exhibit exactly the same behavior at the CEXT pin, although the CEXT voltage is abnormal in all cases.

As ESD protection for the differential pairs, we use the TPD4E05U06DQAR. After the surge test, we confirmed that the TVS device was not damaged. The TPD4E05U06DQAR survived the surge, while the analog portion of the DP83826I was damaged.

The schematic of the Ethernet section and the RJ45 MagJack used in our design are attached.

We would appreciate any suggestions or recommendations on what could be causing this failure, particularly why the analog portion of the PHY is affected while the digital portion remains fully operational. Could you also advise us on what additional measurements or tests you would recommend to help identify the failure mechanism?

Thanks in advance for your support.

Regards,

Jan

RE: DP83826I: DP83826I Analog Portion Failure After ESD Event

Shane Hauser — Thu, 24 Sep 2026 19:38:15 GMT

Hi Jan,

ESD is largely related to the layout design and GND routing/shield GND vs board GND isolation. Are you able to share the layout here? Particularly the segment between the PHY and the RJ-45 connector where the ESD strike is applied.

The magnetics specs don't meet the DP83826A datasheet recommendations, yet if ESD is the only issue I don't think this would have much impact.

For recommendations, I want to be sure that your RJ-45's shield GND is separate from the board GND where the PHY is located. Typically we use a 1Mohm resistor and capacitor in parallel to connect the shield GND to the board GND. You can see how this is done on the DP83826A EVM.

Another recommendation I have is to switch from DP83826I to DP83826AI. DP83826A... is the newer variant of DP83826 with more robust ESD performance.

Best,

Shane

DS90UB960-Q1: FPD3 MODE: Clarification on the FPD3 MODE values in the datasheet

Sachin Chandran — Thu, 17 Sep 2026 15:44:00 GMT

Part Number: DS90UB960-Q1

Hello Team,

I would like to get some clarification on the FPD3 MODE based on the DS90UB960-Q1 datasheet.

As per the datasheet the below modes are possible for the MODE PIN:

But in register 0x6D, we only have 2 bits allocated for FPD3 MODE, meaning the MODE can be modified to only 4 MODES (see fig below)

There is another register 0xB8 to read the MODE (see below)

We would like to know how to interpret the data to understand how the MODE is set and how to read it to identify the current MODE the pin is strapped to.

2. Also if the pin is not latched to the required MODE, is it possible to simply over-ride via register 0x6D? or do we have to perform any reset for the deser?

RE: DS90UB960-Q1: FPD3 MODE: Clarification on the FPD3 MODE values in the datasheet

Caitlin Behne — Thu, 24 Sep 2026 19:14:44 GMT

Hello Sachin,

You're welcome, let me know if you have any further questions.

Best regards,
Caitlin Behne

RE: TPS66020: Can you get me Datasheet for tps66993?

Elijah Orozco — Thu, 24 Sep 2026 18:43:10 GMT

Hi Wayman,

The datasheet can be accessed at Secure resources | TI.com

Best,

Elijah

TPS66020: Can you get me Datasheet for tps66993?

Wayman Sit — Mon, 21 Sep 2026 20:47:55 GMT

Part Number: TPS66020

Need datasheet for tps66993

DS250DF810: Design Collaterals Requests

Gabriel Melendez — Thu, 24 Sep 2026 14:49:43 GMT

Part Number: DS250DF810

Can I get a copy of the following design collaterals?

DS280DF810_MW_Rev3-01-23-2015.pdf

DS280XX810_EVM_BRD_REVC_15-0024_PCB_030615-1.brd

DS280XX810_EVM_BRD_REVC_15-0024_GBR_031915-1.zip

RE: DS250DF810: Design Collaterals Requests

Charles — Thu, 24 Sep 2026 18:28:13 GMT

Please request for the collateral in the secure folder:

Thank you,

Charles

RE: DS160PR410: Regarding the IBIS-AMI model and EQ s-parameter settings of the DS160PR410

Charles — Thu, 24 Sep 2026 18:26:21 GMT

Hi Shuhei,

S-parameter and IBIS-AMI models have been independently correlated to measured bench results. Using s-parameter should be representative of real-world performance.

Thanks,

Charles

DS160PR410: Regarding the IBIS-AMI model and EQ s-parameter settings of the DS160PR410

shuhei hayashi — Thu, 24 Sep 2026 09:02:35 GMT

Part Number: DS160PR410

Hi All,

Previously, I received a response from TI stating that if the IBIS-AMS model for the DS160PR410 was unavailable, it would be acceptable to substitute it with the IBIS-AMS model for the DS160PR810.
However, the customer's policy has changed, and they now plan to perform analysis using an S-parameter model for the EQ instead of the IBIS-AMI model.
Would you kindly tell me whether the EQ settings for the S-parameter model and the IBIS-AMI model of the DS160PR410 are equivalent?
Also, can the simulation result obtained using the DS160PR410 EQ s-parameter model be considered equivalent to a simulation using the DS160PR410 IBIS-AMI model?

Best Regards,
Shuhei Hayashi,

RE: DS90UB960-Q1: FPD3 MODE: Clarification on the FPD3 MODE values in the datasheet

Sachin Chandran — Thu, 24 Sep 2026 16:47:10 GMT

Thanks Caitlin, we will check and get back to you

THVD9491-SP: Information about ordering non-space test units

CJ Long — Thu, 24 Sep 2026 15:29:20 GMT

Part Number: THVD9491-SP

Hello,

For the above part number, I noted that the dev kits are much cheaper than the prices for the fully qualified parts. Is there a way to order non-qualified versions for development, so we can mount those on our PCB, without having to use the space grade parts for everything? I noted that SN65HVD1476DR, while not completely, identical, appears to be pin compatible enough to work in a pinch. However, we would prefer to prototype with the correct part. What is the correct path forward? Can we order the space parts without some of the certifications?

RE: THVD9491-SP: Information about ordering non-space test units

Ethan Sempsrott — Thu, 24 Sep 2026 16:09:39 GMT

Hi CJ,

If you just want another device for testing/prototyping, I would use the THVD2452V-EP. This has the same pinout and RS-485 functionality without the space rating. So you can just solder/desolder this device on the same board you intend to use with the space version.

But for any specific validation/characterization, the THVD9491-SP should be used of course. Note that for edge case testing, like max data rate/max cable length/max node count, the THVD9491-SP should be used.

Best,

Ethan