https://e2e.ti.com/support/interface-group/interface/<p style="display:none;">blank</p>en-USTelligent Community 13https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1676512/dp83867e-mdi-interface-speed-automatically-follow-the-speed-of-the-88q2112/6466696Fri, 28 Aug 2026 21:16:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:94977720-f4ec-466a-bcec-10fd1b349376Gerome CachoDanilo, The DP83867 PHY cannot be configured to speed adapt based on SGMII. In actuality, since PHY to PHY communication is not the original intended purpose of SGMII (instead PHY-MAC), the speed of the MAC should adapt to the PHY&#39;s MDI. Going back to the dual PHY configuration, as these are multi-speed, there must be software configured to either constrain application to single speed, or switch the other device to accommodate specific speed as needed. Sincerely, Geromehttps://e2e.ti.com/support/interface-group/interface/f/interface-forum/1677137/dp83822hf-questions-regarding-dp83822if-100base-fx-and-sfp-interface-for-ethercat/6466689Fri, 28 Aug 2026 21:11:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:3b02db80-a6b6-4f41-af37-037e15a911daGerome CachoHi Shimizu-san, The 49.9 ohm PUs are required for the current mode drivers within the DP83822. Please consider this as part of the SERDES IC block itself if reference Figure 2B in 8074i. Sincerely, Geromehttps://e2e.ti.com/support/interface-group/interface/f/interface-forum/1677517/tdp158-successor-of-this-ics/6466683Fri, 28 Aug 2026 21:03:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ff9c2dcd-ccb7-4f1c-a9b0-ce5b3bbb57dbDavid (ASIC) LiuAndreas With the introduction of the HDMI2.1 specification, HDMI now supports both AC coupling and DC coupling implementation for a source side design. And with the upcoming release of HDMI2.2, most likely any new design will go with AC coupling implementation from signal integrity perspective. So besides the xx1204 re-drivers, we also introduced TDP2004 as a HDMI2.1 Source Side AC Coupled Linear Re-driver. The TDP2004 offers higher bandwidth than xx1204 in order to support the upcoming HDMI2.2 24Gbps. With HDMI2.1 also introducing link training and re-timer may impact the success of link training, we also decided to focus more on the linear re-driver development as linear re-driver does not impact the link training. So at this moment we have xx1204 (support up to HDMI2.1, AC/DC coupling implementation), and TDP2004 (current support to HDMI2.1 with future support up to HDMI2.2, AC coupling implementation only). Thanks Davidhttps://e2e.ti.com/support/interface-group/interface/f/interface-forum/1677605/pci2050b-pci2050bzwt-nfbga-25-pin-define-check-for-datasheet-vs-symbol/6466665Fri, 28 Aug 2026 20:52:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:dc75f0c7-41fd-4822-aad5-3d083806ae4dDavid (ASIC) LiuHi, Please follow the PCI2050B datasheet I/O definition. Thanks Davidhttps://e2e.ti.com/support/interface-group/interface/f/interface-forum/1676634/ds80pci402-sch-review/6466662Fri, 28 Aug 2026 20:50:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:30c22081-961c-47c3-bc71-68944ff52f59Vivaan JaiswalHi Leo, Here are my comments ENSMB pin strapped to pin mode, meaning no SMBus access Both EQ and DEM settings set to Level 6 Rate set to Gen 3 without Demphasis PRSNT pin PD to GND using 20kOhms. Ensure that this pin reads low for proper functionality RXDET left floating for default termination setting LPK set to normal operation, no loopback VDD SEL set to 3.3V Mode Signal Detect Threshold left at default Do not connect 3.3V to VDD pin. In 3.3V Mode, these pins are required to have 0.1uF capacitors since they are the output of the internal regulator Best, Vivaanhttps://e2e.ti.com/support/interface-group/interface/f/interface-forum/1677160/dp83867cr-dp83867crrgz-does-not-establish-ethernet-link-on-custom-board/6466651Fri, 28 Aug 2026 20:43:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:19e7f9e5-bc17-4bac-8525-8095680fd9ebGerome CachoHi Conor, It appears that PHY is alive and clocking appropriately from spotcheck. Can you please provide a dump of 0x0-0x1F and 0x6E and 0x6F? Note the last two are extended registers and need Reg 0xD/0xE 4 step process to access. It is okay to leave VDDA1P8 pins disconnected. I am curious if mirror mode is needed. Could you try and either strap with this or enable via registers? Sincerely, Geromehttps://e2e.ti.com/support/interface-group/interface/f/interface-forum/1677155/onet1191v-onet1191p-a-high-speed-3-3v-limiting-amplifier-eol/6466633Fri, 28 Aug 2026 20:26:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:0d1226dc-91c9-4595-92e3-09ce30f36098Drew Miller1Hi T, I will follow up with you over email. Thanks, Drewhttps://e2e.ti.com/support/interface-group/interface/f/interface-forum/1677322/dp83825i-rmii-lengths-and-impedance/6466592Fri, 28 Aug 2026 19:43:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2a875b52-b47a-4f6a-8533-e7bf9a0902edShane HauserHi Jared, 1. Similar to this E2E RMII traces should all match to the reference clock. 2. Yes this includes TX_EN 3. Yes this includes CRS_DV 4. Trace lengths under 2&quot; are ok. Having a very short trace length can make component placement difficult. How short of a trace are you planning to use? 5. Impedance matching minimizes signal reflections caused from impedance discontinuity. Signal reflections are not great for signal quality or EMI emissions. Best, Shanhttps://e2e.ti.com/support/interface-group/interface/f/interface-forum/1674211/tusb8041-can-tusb8041irgcr-set-eq-and-how/6466576Fri, 28 Aug 2026 19:28:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:cb9063fc-3aa8-47c3-a33c-47bd4f5b59c5Brian Zhouany update? Best Brianhttps://e2e.ti.com/support/interface-group/interface/f/interface-forum/1677579/tps26750-usb-pd-controller-required/6466568Fri, 28 Aug 2026 19:22:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2729c9a9-500f-47e0-9c0a-6bff3223849eAdrian Sacalxot-BerriosHi Vaishak, 1. TPS26750A can support up to 48V when paired with our protection device, TPD4S480. 2. We currently do not have any non-automotive devices in our portfolio that can support display port. What application are you looking to implement Display port in? Thanks, Adrianhttps://e2e.ti.com/support/interface-group/interface/f/interface-forum/1677243/esd2can36-q1-tcan1057-esd-protection/6466553Fri, 28 Aug 2026 19:13:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9a8ced3b-b4e3-4fe5-85ef-127ec6eac0ccBryan Rodriguez de San MiguelHi Haiwen, We have to ensure that the ESD2CAN36-Q1 clamping voltage is lower than the abs max rating of the transceiver we are protecting. In this case it is very close which is why I would recommend a higher abs max rating CAN transceiver &quot;H&quot;. We are also releasing a ESD2CAN27-Q1 in 4Q which you could also potentially use in this application, and its clamping voltage is below the 58V abs max rating of your transceiver. Best, Bryanhttps://e2e.ti.com/support/interface-group/interface/f/interface-forum/1677622/tusb2e221-qualcomm-tusb2e2211-gl852gt-usb2-hub-issue-discussion/6466549Fri, 28 Aug 2026 19:11:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:c4556270-fcae-46fa-a113-2aa6a7e211b3Ryan KittoHi Kai, Ken, Looking at the waveforms provided, I don&#39;t see why the Port Configuration or XeSE1 is being ruled out. Going by the auto-resume process, there should be no reason for the repeater to be prompted to reset. Where that blue pulse is, I would expect to see SOResume instead of a reset. I would like to clarify whether the signal in the blue highlight is meant to be SOR or a Reset, and if it is meant to be XeSE1 for Reset instead of a SOR, why is that? What would prompt this from the host? Going by what we see in the waveforms, the activity up until that blue highlight is in-line with what is expected for the auto-resume process: [quote userid=&quot;464498&quot; url=&quot;~/support/interface-group/interface/f/interface-forum/1677622/tusb2e221-qualcomm-tusb2e2211-gl852gt-usb2-hub-issue-discussion&quot;] Success with another hub: [/quote] It does look like in this waveform that the pulse on D+ is absent. However, D+ stays high, which would indicate to me that it is still in a suspend state potentially. I would expect to see an SE0 state that is followed by D+ going high, which should indicate EOR and a successful auto-resume: With this other hub, does the issue with power-saving mode disappear? Does the hub stay enumerated at all times and no longer disconnects? If switching hubs resolves the issue, this would lead me to believe this could be an issue with the US port of the hub. Our repeater will not send any pulse on D+ while driving D-. Thanks, Ryanhttps://e2e.ti.com/support/interface-group/interface/f/interface-forum/1676221/pspice-for-ti-need-pspice-model-for-parts-tpd6e001rser-tpd4e05u06dqar-tpd6f003dqdr/6466547Fri, 28 Aug 2026 19:09:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:3145045f-2720-4c55-98ee-88b4bd0889b4Bryan Rodriguez de San MiguelHi Aman, See the TPD4E05U06 PSPICE library attached. e2e.ti.com/.../TPD4E05U06_2D00_Q1.lib We currently do not have the other PSPICE models available. Best, Bryanhttps://e2e.ti.com/support/interface-group/interface/f/interface-forum/1677627/sn55lvds33-sp-inquiry-regarding-minimum-conductor-spacing-for-sn55lvds33-sp-5962-0724801vfaFri, 28 Aug 2026 17:39:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:46338c7f-7e4c-47c2-becc-c08e03f0f312KENJI OTAKEPart Number: SN55LVDS33-SP Dear TI Team, We have received a technical inquiry from our customer regarding device 5962-0724801VFA (SN55LVDS33-SP). PO: PO2408049 Qty: 418 Packing slip and CofC attached. TI PO2408049 5962-0724801FVA DC2339A.pdf The customer performed a PIND test and identified an approximately 40 &#181;m conductive particle inside one device. During their subsequent analysis, they reviewed DPA images and estimated the minimum conductor spacing within the package to be approximately 70 &#181;m. Based on this observation, they believe the particle would not be capable of causing an electrical short. However, their end customer has requested confirmation from TI. Could TI please advise: 1. Whether the minimum conductor spacing (worst-case design value) for this device can be disclosed; or 2. If the spacing cannot be disclosed due to proprietary design restrictions, whether TI can provide an engineering assessment or statement regarding the likelihood of a 40 &#181;m conductive particle causing an electrical short within the package. SN55LVDS33-SP.pdf We understand that detailed design information may be proprietary and not releasable. Any technical guidance or statement addressing the customer&#39;s concern would be greatly appreciated. Thank you for your support. Best regards, Kenji Otake Fuji Electronics America, Inc.SN55LVDS33-SPhttps://e2e.ti.com/support/interface-group/interface/f/interface-forum/1677557/tps65987d-questions-regarding-the-patch-file-of-tps65987ddh-currently-used-in-production/6466419Fri, 28 Aug 2026 16:46:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ca60286d-d6fd-4dac-96c0-623c021639deElijah OrozcoHi Kyohei, A team member will respond to you shortly. Best, Elijahhttps://e2e.ti.com/support/interface-group/interface/f/interface-forum/1677622/tusb2e221-qualcomm-tusb2e2211-gl852gt-usb2-hub-issue-discussionFri, 28 Aug 2026 16:32:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:810ffb62-87bf-4112-a747-50c90b6e4356Kai LaiPart Number: TUSB2E221 Hi Team, Please see below for questions from QC. After comparing all the waveforms from log provided, let me share our analysis here. The waveforms we have: Fail: 2026-08-11_09-56-02.kvdat e2e.ti.com/.../2026_2D00_08_2D00_11_5F00_09_2D00_56_2D00_02.kvdat Success with another hub: EUSB5_SMSC HUB.kvdat Success bypass the hub: EUSB5 power saving on_bypass hub.kvdat No matter in fail or success waveforms, EUSB+ always triggers the pulse in blue at first. And USB+ behavior looks normal in all the success waveforms. In this way, we don&#39;t think the pulse in blue is the root cause. The pulse in blue doesn&#39;t affect Port/Repeater Configuration. However, in the fail waveform, USB+ triggers the pulses in white when the timeline is around 10ms. And it keeps repeating after that to do resets. But EUSB+ never triggers the pulses in white at the same time. In this way, the pulses in white are triggered either repeater side or hub side. Could you help to check on this? Fail: Success with another hub: Success bypass the hub:TUSB2E221https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1677379/tusb319-q1-schematic-review-with-hd3ss3212rksrq1/6466351Fri, 28 Aug 2026 15:42:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:78aff5e6-5169-4612-9d47-7d0f2265ea05Ryan KittoHi Han, If the current needed is 500/900mA, the CURRENT_MODE pin can be left floating. PD resistor works as well though. For the CC pins, Why are there PD caps on the CC pins? Are these for discharge? And just to confirm, is the Source pin of the MOSFET meant to be connected to ground, and not the CC pins? Typically we recommend against ESD diodes on the CC lines, as these can affect CC negotiation. Is the MOSFET meant to be used with the ID pin of the CC controller to invert the ID pin? Please keep in mind that while the ID pin is high, VBUS should NOT be sent. VBUS should only be sent to the type-C connector when the ID pin is low. Please ensure VBUS is only sent when the ID pin is low. Why is the DIR pin pulled up to two different voltage rails? Will only one of these rails be enabled at a time? Thanks, Ryanhttps://e2e.ti.com/support/interface-group/interface/f/interface-forum/1677605/pci2050b-pci2050bzwt-nfbga-25-pin-define-check-for-datasheet-vs-symbolFri, 28 Aug 2026 15:32:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:f9748f28-7ddf-4175-8fc1-30cb8c605826Sean Liao (Yu-Sheng)Part Number: PCI2050B Hi sir, Customer found PCI2050BZWT(NFBGA-25) I/O Type is different in datasheet vs the OrCAD symbol Should we follow datasheet? https://vendor.ultralibrarian.com/TI/embedded/?gpn=PCI2050B&amp;package=ZWT&amp;pin=257&amp;sid=019f5f328119000fb09089f449940506f02cb06700bd0&amp;c=1 NO NAME SPEC Page15 &amp; 16 &amp; 21~26 Symbol A11 S_DEVSEL Bidirectional Passive B11 S_TRDY Bidirectional Passive B12 S_STOP Bidirectional Passive B13 S_SERR Input Passive B4 S_REQ0 Input Bidirectional C11 S_IRDY Bidirectional Passive C12 S_LOCK Bidirectional Passive C13 S_PAR Bidirectional Passive E1 S_REQ5 Input Bidirectional E12 S_PERR Bidirectional Passive E17 MS0 Input Bidirectional E18 S_M66ENA Bidirectional Passive E2 S_REQ4 Input Bidirectional E3 S_REQ1 Input Bidirectional F1 S_GNT0 Output Bidirectional F11 S_FRAME Bidirectional Passive F2 S_REQ7 Input Bidirectional F3 S_REQ6 Input Bidirectional F5 S_REQ2 Input Bidirectional G1 Output Bidirectional S_GNT3 G2 S_GNT2 Output Bidirectional G5 S_REQ8 Input Bidirectional G6 S_REQ3 Input Bidirectional H1 S_GNT7 Output Bidirectional H2 S_GNT6 Output Bidirectional H3 S_GNT5 Output Bidirectional H5 Output Bidirectional S_GNT4 H6 Output Bidirectional S_GNT1 J1 Output Bidirectional S_GNT8 J17 S_VCCP Power Passive J18 TRST Input Passive J19 TCK Input Passive J3 S_CLK Input Passive J5 S_RST Output Passive J6 S_CFN Input Passive K1 HS_SWITCH/GPIO3 Bidirectional Passive K14 TMS Input Passive K17 TDO Output Passive K18 TDI Input Passive L14 HS_LED Output Passive L15 HS_ENUM Output Passive L17 MSK_IN Input Passive L18 CONFIG66 Input Passive L19 P_VCCP Power Passive N5 BPCCE Input Passive P11 P_TRDY Bidirectional Passive P12 P_LOCK Bidirectional Passive P2 P_RST Input Passive P3 P_CLK Input Passive P6 P_REQ Output Passive R1 P_GNT Input Passive R11 P_DEVSEL Bidirectional Passive R12 P_PERR Bidirectional Passive T19 MS1 Input Bidirectional U11 Bidirectional Passive P_IRDY V13 P_PAR Bidirectional Passive W11 P_FRAME Bidirectional Passive W12 P_STOP Bidirectional Passive W13 P_SERR Output Passive W16 P_M66ENA Input Passive W7 P_IDSEL Input PassivePCI2050BDatacom modulehttps://e2e.ti.com/support/interface-group/interface/f/interface-forum/1677371/tusb2e221-eq-setting/6466326Fri, 28 Aug 2026 15:23:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:7f0c048a-6504-424f-b792-22422256515bRyan KittoHi Jeff, Correct, Table 5-5 details how to set the compensation level using the EQ pins, and which level to select based on your ESR. Table 5-6 essentially takes those same compensation levels and details how the actual I2C register values correlate. Please keep in mind if you are using GPIO settings that the eUSB2 and USB2 PHYs are configured exclusively. Only one PHY can be configured at a time in GPIO mode, not both. Thanks, Ryanhttps://e2e.ti.com/support/interface-group/interface/f/interface-forum/1673544/tca9536-io-controll/6466277Fri, 28 Aug 2026 14:39:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:e6d02fa3-554b-4ae5-a8c3-a1617fff1741Tyler TownsendHi Jeff, This is an I2C controlled I/O expander. The I/O pins will power up as INPUT&#39;s. The state change to P0 or P1 would happen externally to whatever is connected to the pin. Regards, Tyler