https://e2e.ti.com/support/interface-group/interface/<p style="display:none;">blank</p>en-USTelligent Community 13https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1666828/ds90ub9702-q1-ds90ub9702-q1-datasheet-and-reference-design/6427783Fri, 24 Jul 2026 03:53:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:063d30ba-eda0-479e-bbb5-c42bb20432d3Logan CumminsHi Xiang, If you go to the 9702 product page, there is a access request for design folders for full collateral access. This will be granted after verifying required NDAs are in place for these parts. www.ti.com/.../DS90UB9702-Q1-DESIGN Regards, Loganhttps://e2e.ti.com/support/interface-group/interface/f/interface-forum/1667189/tps25751-gpio-thresholdFri, 24 Jul 2026 03:15:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:bc65a089-3e42-49f1-9513-fc6fd385edaaRoy Chou1Part Number: TPS25751 Hi Team, Would you let me know the threshold of GPIOs? Thank you. Regards, RoyTPS25751PC &amp; Notebookshttps://e2e.ti.com/support/interface-group/interface/f/interface-forum/1662610/ds90ub947-q1evm-how-t-configre-dual-oldi-mode/6427722Fri, 24 Jul 2026 02:27:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ef2e2329-5be4-4970-afc6-6223e3f7fd9euser4779049Nikolas-san, Thank you for your reply. I Understood it. Below is a conceptual block diagram. The SoC generates a 1080p60 image. The FPGA then converts this image into two OLDI streams. Each OLDI stream consists of four LVDS lanes (serializing 7 bits each) and a 75 MHz clock. Each OLDI stream simultaneously outputs adjacent odd and even pixels. The Dual OLDI signals output from the FPGA are input into the UB947. The UB948 expects to output the data received by the UB947 in its original format. In other words, if the UB947 and UB948 were bypassed, the Dual OLDI signals output from the FPGA would be input directly into the LCD panel and displayed. So, the binput clock frequency and output clock frequency must be same. Mitahttps://e2e.ti.com/support/interface-group/interface/f/interface-forum/1665971/tcan1575-q1-ilkg-of-inh-pin/6427704Fri, 24 Jul 2026 02:03:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ecd51a81-34f3-4c99-bbea-60a32fd04574Shinji TsujiHi Sean-san, I thought ILKG(OFF) is the off leakage spec of the high side internal pull up switch between INH pin and Vsup, is my understanding correct? regards,https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1666403/tvs5200-different-datasheet-tvs4000-in-the-tvs5200-folder/6427629Thu, 23 Jul 2026 23:44:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:0763ad87-49e3-4417-a854-2bfea50102cfShinichi InoueHi Bryan, Thank you for your reply. Today I confirmed with the URL of TVS5200 product folder below, the situation remains the same. Only HTML version is able to obtain TVS5200 datasheet. https://www.ti.com/product/TVS5200?keyMatch=TVS5200&amp;tisearch=universal_search&amp;usecase=GPN Could you please confirm and solve the issue? I appreciate your great help and cooperation. Best regards, Shinichihttps://e2e.ti.com/support/interface-group/interface/f/interface-forum/1659515/tps4816-q1-schematic-check/6427596Thu, 23 Jul 2026 23:04:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2f454ea2-d5b5-4411-b01a-dbdd8a639513Sarah RainesCan you also confirm the other questions? Thanks, Sarahhttps://e2e.ti.com/support/interface-group/interface/f/interface-forum/1660390/ds90ub953-q1-csi_err-flags-at-low-temperatures/6427568Thu, 23 Jul 2026 22:22:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:f3f53d92-c6aa-4daa-8f51-386357eab466Gerald StierEthan, Let me provide some more details I had our tech run the test three times on two different cameras, reinitializing the camera between each test While some tests came back clear, both eventually had CSI-related errors during the soak in the chamber. The register content was not the same each time. For completeness, I will list the register contents for the SER/DES on each trial Unit 09 - Trial 1: CSI_ERR_CNT (0x5C) = 0x00 CSI_ERR_DLANE01 (0x5E) = 0x00 CSI_ERR_DLANE23 (0x5F) = 0x00 SENSOR_STS_0 (0x51) = 0x28 SENSOR_STS_3 (0x54) = 0x00 Unit 09 - Trial 2: CSI_ERR_CNT (0x5C) = 0x24 CSI_ERR_DLANE01 (0x5E) = 0x02 CSI_ERR_DLANE23 (0x5F) = 0x06 SENSOR_STS_0 (0x51) = 0x28 SENSOR_STS_3 (0x54) = 0x00 Unit 09 - Trial 3: CSI_ERR_CNT (0x5C) = 0x01 CSI_ERR_DLANE01 (0x5E) = 0x44 CSI_ERR_DLANE23 (0x5F) = 0x44 SENSOR_STS_0 (0x51) = 0x28 SENSOR_STS_3 (0x54) = 0x00 Unit 10 - Trial 1: CSI_ERR_CNT (0x5C) = 0x00 CSI_ERR_DLANE01 (0x5E) = 0x00 CSI_ERR_DLANE23 (0x5F) = 0x00 SENSOR_STS_0 (0x51) = 0x28 SENSOR_STS_3 (0x54) = 0x00 Unit 10 - Trial 2: CSI_ERR_CNT (0x5C) = 0x00 CSI_ERR_DLANE01 (0x5E) = 0x02 CSI_ERR_DLANE23 (0x5F) = 0x00 SENSOR_STS_0 (0x51) = 0x28 SENSOR_STS_3 (0x54) = 0x00 Unit 10 - Trial 3: CSI_ERR_CNT (0x5C) = 0x25 CSI_ERR_DLANE01 (0x5E) = 0x06 CSI_ERR_DLANE23 (0x5F) = 0x06 SENSOR_STS_0 (0x51) = 0x28 SENSOR_STS_3 (0x54) = 0x00 Before these tests and activating PATGEN, OVT10652 register was set 0x3012 = 0x00, to end streaming and put the chip into standby. I will have our tech try another test where the Imager is set into a Power Down state instead of a Standby state to see if there is a difference in behavior. While rerunning the test, I will record the contents of 0x7B and report backhttps://e2e.ti.com/support/interface-group/interface/f/interface-forum/1667044/sn65lvds93a-sn65lvds93a-for-cameralink-interface/6427560Thu, 23 Jul 2026 22:19:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:d0f0206c-4f4c-4660-aacf-491a7fbbc56bIkram HaqueHi Anil, 1. The device simply serializes LVTTL with RGB and HS/VS/DE data input to LVDS output. So this can be used for the conversion. Reference for RGB to OLDI converion mapping: https://www.ti.com/lit/an/snla014a/snla014a.pdf? However, whether it can work with your system and &quot;CameraLink&quot; will depend on factors such as cable length and signal integrity. What do you mean by CameraLink? Is there a cable used? How long is it going to be and is it rated for LVDS or OLDI signal transmission for all the differential pairs? 2. The LVDS93A device converts RGB/TTL to LVDS. Please check whether the input of the CameraLink, or frame grabber is compatible with LVDS or OLDI. 3. This part is validated for the specifications shared in the datasheet for LVDS output. If the CameraLink, frame grabber, display, SoC, etc you are using are compliant for openLDI or LVDS video interface, then it should be compatible. 4. On your application are you using cable and connector, or is the transmission on the same board? I will check whether a BGA part is available for the SN65LVDS93A and get back to you. Best regards, Ikramhttps://e2e.ti.com/support/interface-group/interface/f/interface-forum/1667049/tusb7340-pci-usb-converter-unresponsive-with-septentrio-receiver/6427547Thu, 23 Jul 2026 22:10:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:c95110ee-4e39-47f3-b7f6-1f0fedecde9cVishesh PithadiyaHi, Can you share a schematic of your implementation?https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1645330/dp83848i-about-the-behavior-of-sni-mode/6427541Thu, 23 Jul 2026 22:05:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:87734d45-5d9d-406c-95c6-90293d25355fGregory KobyakovHi Ryu, I will discuss all of the current information about this case with my team, and will give advice on next steps tomorrow. Best regards, Greghttps://e2e.ti.com/support/interface-group/interface/f/interface-forum/1666593/dp83822h-link-failure/6427539Thu, 23 Jul 2026 22:04:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:c8fdb56b-c989-42f4-a6bf-9e51ec2739e6Gregory KobyakovHi Imai-san, If auto-negotiation was disabled on the link partner PHY and enabled on the DP83822 by setting register 0x0[12] = 1, the two PHYs would likely not be able to link-up correctly. It is not normal to get Link Fail when bit 12 of register 0x000 is set to 0, but this could be caused by a difference in speed selection on the two link partner PHYs. Best regards, Greghttps://e2e.ti.com/support/interface-group/interface/f/interface-forum/1667031/dp83tc815-q1-phyloopback-mode-register-set-for-dp83tc815/6427533Thu, 23 Jul 2026 21:59:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:6d39be07-d60e-4351-a7a5-ded7992e2ab5CharlesAnnwesa, Please follow full loopback configuration instructions listed in the datasheet. Best, Charleshttps://e2e.ti.com/support/interface-group/interface/f/interface-forum/1665699/dp83848q-q1-dp83848q-q1-in-rmii-10base-t-rx-elasticity-buffer-underflow-rbr-rx_unf_sts-causes-packet-loss---no-way-to-configure-rbr-elast_buf-in-the-driver/6427494Thu, 23 Jul 2026 21:25:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:0b4d7dfc-8b0b-495b-971d-a0d27f84b030Evan MayhewHi Vikranth, I will share local patch early next week. Upstream is likely in beginning of 2027. Thank you, Evanhttps://e2e.ti.com/support/interface-group/interface/f/interface-forum/1665971/tcan1575-q1-ilkg-of-inh-pin/6427394Thu, 23 Jul 2026 19:34:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:d55481eb-15eb-404a-b138-d273d325ac02Sean GuoHi Shinji, Compared to TCAN1043, the partial networking CAN devices have a weaker pulldown value. Using that spec it is estimated &#177;0.25 uA. Regards, Seanhttps://e2e.ti.com/support/interface-group/interface/f/interface-forum/1664668/tpd12s016-device-status/6427389Thu, 23 Jul 2026 19:29:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:198e3291-9c9c-4bca-b056-3790c3fec71aEthan FrommerHi Adrian, Can you advise why this device is marked NRND?https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1665953/dp83td510e-evm-dp83td510e-media-converter-using-dp83825i/6427367Thu, 23 Jul 2026 19:17:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:25607809-fbc0-4e1d-b022-647e47c8cdbeVivaan JaiswalLet&#39;s continue the conversation over email. I will be closing this thread for now.https://e2e.ti.com/support/interface-group/interface/f/interface-forum/1666403/tvs5200-different-datasheet-tvs4000-in-the-tvs5200-folder/6427360Thu, 23 Jul 2026 19:13:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:3a154855-5a88-4345-bf81-11305fad10abBryan Rodriguez de San MiguelHi Shinichi, I opened all the links that you shared, and I do not see a TVS4000 DS. Where are you located? Maybe the version you are seeing is different. Best, Bryanhttps://e2e.ti.com/support/interface-group/interface/f/interface-forum/1666226/lmh0340-support-request-hd-sdi-interface-using-i-mx8m-plus-lvds-outpu/6427319Thu, 23 Jul 2026 18:42:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:e1cdaf24-c2e2-4fc7-83f0-99e9d76567ceDavid (ASIC) LiuSamudralankaiah I can only speak for TI SDI Serializer as I am not familiar with Semtech solution. For TI SDI serializer, LMH0040/0050/0340/0341 devices are all FPGA assisted SDI serializer/deserializers. FPGA must be used to enable SDI video framing and compatibility. Thanks Davidhttps://e2e.ti.com/support/interface-group/interface/f/interface-forum/1666451/tmds1204-failure-of-i2c-detection/6427305Thu, 23 Jul 2026 18:32:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:4c8b1c58-81e9-4d33-88f3-398838b8438dDavid (ASIC) LiuIrfan We tested the TMDS1204 and verified it is correctly responding to the I2C address according to its strapping value. Any chance you can capture the I2C bus waveform when trying to read the TMDS1204 register? I want to check and make sure there is no setup and hold timing violation on the I2C bus. Thanks Davidhttps://e2e.ti.com/support/interface-group/interface/f/interface-forum/1665500/tps1689evm-tsp1689-evm-cml-error-stuck/6427263Thu, 23 Jul 2026 17:56:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:1edab499-b6ba-4815-8d2e-19e5cea17b2fOssama El-JamalStill havent resolved this issue.