Other Parts Discussed in Thread: LP3470
If the TPD1S514-1 is always enabled how does one ensure that one meets the Inrush Current requirements for USB 2.0/3.0
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Dear Chuck,
Does TI have any efuse / load switch that has the same protection as TPD1S514 and protects against the Inrush Current WITHOUT USING THE AN ENABLE PIN ?
Thanks
Shmuel
Dear Chuck,
Thanks this sounds good however I think I will need a logic inverting gate with this as the Reset of this device will be high when powered ? Do you have a similar device that gives a low voltage when powered ?
Or better yet - Is there any reason I can't use an logic Inverting gate that is +5V compatible and use it to enable the TPD1S514-1 ?
Best regards
Shmuel
This circuit might be a better option than adding another gate to control the enable. It will hold enable high until VBUS_POWER has risen enought to turn the nmos on. This circuit as drawn will toggle when the RC node reaches the VT of the NMOS. I would also add a resistor in parallel with the capacitor to ensure that the nmos does not turn on until VBUS_POWER is greater than 1.2V(VIH) for the enable pin. This should work well for what you are describing.
Please let me know if I can help any further
Regards,
Chuck
If a run a SPICE simulator on the circuit you suggested - would the enable pin staying high for 200nS be enough \ ideal ? What would be an "ideal" value ?
Is there anything else that I should check on the circuit ?
When you run your spice simulations, make sure to vary the resistors across the expect variation of 5% and if you have them use the process min and max models for your transistor. I would also assume a 60% variation in your capacitor unless you have a know very high quality capacitor.
If you use these wide simulation ranges, then 200nS will be ideal for the worst case delay. If you are running a simple nominal simulation with nominal supplies, then I would target 1uS so that you have a lot of system margin.
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Dear Chuck,
Thanks for all your help. I am now using a Spice simulator to work out the appropriate components as you suggested.
Are you able to help me with something similar ?
In my device I have 2 USB ports. The first one is for power and communication. For this port I am using the TI TPD1S514-1 and the circuit you outlined to control the enable pin as we spoke about.
I need the same sort of circuit for my 2nd USB port which is to be used for additional supplementary power and no communication. However it has a slightly different specification requirements. For simplicity the first USB port I call the COMM port and the 2nd is the PWR port.
For this 2nd PWR port I also need to deal with the enable of TPD1S514-1 once the PWR port is providing power so that I can utilize the inrush current feature of the TPD1S514-1. However this PWR port is only to be enabled when the COMM. port is active (plugged in). Thus I was thinking of using a similar circuit to what you suggested but using the VBUS_SYS voltage from the COMM port as an additional enable ! The catch is for the PWR port the enable will have to full fill the following 3 scenarios :-
1. PWR port connected, COMM port not connected : Enable pin deactivated
2. COMM. port connected and some time later(could be even minutes) the PWR port is connected : Enabled pin activated
3. PWR port connected and some time later(could be even minutes) the COMM port is connected : Enabled pin activated
I was thinking of using a 2nd nMosfet so that I could save on the parts - is this possible ?
Thank you so much in advanced !
Best regards
Shmuel