This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPD1S514: Always Enabled & Inrush Current

Part Number: TPD1S514
Other Parts Discussed in Thread: LP3470

If the TPD1S514-1 is always enabled how does one ensure that one meets the Inrush Current requirements for USB 2.0/3.0

  • Shmuel,

    In this case, the battery charger or some other power switch in the system would need to provide current limiting to ensure that that USB spec is met.

    Regards,
    Chuck
  • Dear Chuck,

    Does TI have any efuse / load switch that has the same protection as TPD1S514 and protects against the Inrush Current WITHOUT USING THE AN ENABLE PIN ? 

    Thanks

    Shmuel

  • Shmuel,

    I could not find a single device that is equivalent to the TPD1S514 without the enable pin.

    If your budget allows for an additional circuit, you could add a LP3470 power supply reset generator ( www.ti.com/.../lp3470 that is powered by the VBUS_POWER pin to control the enable pin. This will create an autonomous interface that I believe will do what you need in your system.

    Chuck
  • Dear Chuck,

    Thanks this sounds good however I think I will need a logic inverting gate with this as the Reset of this device will be high when powered ? Do you have a similar device that gives a low voltage when powered ?

    Or better yet - Is there any reason I can't use an logic Inverting gate that is +5V compatible and use it to enable the TPD1S514-1 ?

    Best regards

    Shmuel

  • This circuit might be a better option than adding another gate to control the enable.  It will hold enable high until VBUS_POWER has risen enought to turn the nmos on.  This circuit as drawn will toggle when the RC node reaches the VT of the NMOS.  I would also add a resistor in parallel with the capacitor to ensure that the nmos does not turn on until VBUS_POWER is greater than 1.2V(VIH) for the enable pin.  This should work well for what you are describing.

    Please let me know if I can help any further

    Regards,

    Chuck

  • I would prefer to use a logic gate to reduce the number of discrete components, and we have one (SC70-5) - it would only require a 0402 cap on the vcc supply and a 0402 pull up resistor to VBUS_Power on the enable pin of the TPD1S514-1.

    Is there any issues that you know of that I might have to be aware of when using this with the TPD1S514-1 ?
  • The only issue I see with the discrete gate is that you will have to ensure that the LP3470 reset period is long enough to guarantee that the logic gate drives the EN pin high before transitioning low. You will have to design the capacitor delay on the LP3470 to understand the logic gate power up sequence.

    The circuit should be robust with proper care.
  • Sorry Chuck - maybe I was not clear

    I was thinking not to use the LP3470 at all and only use an inverting logic gate to give me the low signal I need to enable the TPD1S514-1 after VBUS_Power gave me the +5V ?
  • I think you will need to add an RC delay to ensure that the gate is high for at least a few hundred nano seconds to ensure that the counters that generate the delays in the TPD1S514 properly reset. You will essentially have to implement the nmos circuit I drew without the pull-up resistor.
  • O.K. so I found that we have in stock a 2N7002 N-channel TrenchMOS FET - I assume this will be good enough to implement the nmos circuit you drew. Are you able to do me a favour and provide suggested resistor and cap values ?
  • I don't have a spice model to check the input voltage vs time constant, so I cannot verify my sizes, but here is a good starting place.

    I would start with 10kohm as the drain resistor connected to the VBUS_POWER, a 100nF capacitor with a 1kohm resistor to VBUS power, and a gate to ground resistor if 100kohms. This should give about 1-20uS of time constant to turn the nmos on with resonable component accuracy.

    Regards,
    Chuck
  • Dear Chuck,

    Thanks for all your help

    Best regards

    Shmuel
  • If a run a SPICE simulator on the circuit you suggested - would the enable pin staying high for 200nS be enough \ ideal ? What would be an "ideal" value ?

    Is there anything else that I should check on the circuit ? 

  • When you run your spice simulations, make sure to vary the resistors across the expect variation of 5% and if you have them use the process min and max models for your transistor.  I would also assume a 60% variation in your capacitor unless you have a know very high quality capacitor.

    If you use these wide simulation ranges, then 200nS will be ideal for the worst case delay.  If you are running a simple nominal simulation with nominal supplies, then I would target 1uS so that you have a lot of system margin.

    If you need more help, please reply back. If your question is answered, please click  Verify Answer 

  • Dear Chuck,

    Thanks for all your help. I am now using a Spice simulator to work out the appropriate components as you suggested. 

    Are you able to help me with something similar ?

    In my device I have 2 USB ports. The first one is for power and communication. For this port I am using the TI TPD1S514-1 and the circuit you outlined to control the enable pin as we spoke about.

    I need the same sort of circuit for my 2nd USB port which is to be used for additional supplementary power and no communication. However it has a slightly different specification requirements. For simplicity the first USB port I call the COMM port and the 2nd is the PWR port.

    For this 2nd PWR port I also need to deal with the enable of TPD1S514-1 once the PWR port is providing power so that I can utilize the inrush current feature of the TPD1S514-1. However this PWR port is only to be enabled when the COMM. port is active (plugged in). Thus I was thinking of using a similar circuit to what you suggested but using the VBUS_SYS voltage from the COMM port as an additional enable ! The catch is for the PWR port the enable will have to full fill the following 3 scenarios :-

    1. PWR port connected, COMM port not connected : Enable pin deactivated 

    2. COMM. port connected and some time later(could be even minutes) the PWR port is connected : Enabled pin activated

    3. PWR port connected and some time later(could be even minutes) the COMM port is connected : Enabled pin activated

    I was thinking of using a 2nd nMosfet so that I could save on the parts - is this possible ? 

    Thank you so much in advanced ! 

    Best regards

    Shmuel 

  • Shmuel,

    I believe that this circuit would implement what you intend:

    If this is not what you were thinking, then please send me a diagram of the two devices and I can try to help come up with something.

  • Dear Chuck,
    Thank you.
    To clarify I am looking for a circuit (very similar to the original circuit you suggested which I am using for my COMM port) with a single output that is to feeds into the enable pin of the TPD1S514-1 protecting the PWR port.

    However it can only be enabled when the COMM port is powered. Thus I was thinking of using the VBUS_SYS output of the TPD1S514-1 that is protecting the COMM. port to condition the activation of this output of this circuit that feeds into the enable pin of the TPD1S514-1 protecting the PWR port.

    However I still need the 3 conditions I mentioned in my previous post

    Thank you very much

    Shmuel
  • This circuit will only enable the POWER port when the com port is enabled, but it requires 3 fets to implement the "and" function on the Power port Enable.

    I believe that it meets all 3 of your conditions, as the power is implemented as an and of the comm port enable.

  • Thank you so much for all your help