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SN65DSI83Q1-EVM: LVDS data & clock is not output.

Part Number: SN65DSI83Q1-EVM
Other Parts Discussed in Thread: SN65DSI83


Hello.

Test condition.

LCD : 800*480

using mipi 2lane, 24BPP

LVDS clock is defined by panel as 30MHz.

DSI clock is 180MHz.

CPU : MSM8974

MSM8974 MIPI <-> SN65DSI83Q1-EVM

DSI Channel A <-> LVDS Channel B <-> LCD Panel

SN65DSI83 register control does not change the screen. and LVDS data & clock is not output.

Could you check a code please. what is wrong?

{0x09, 0x00}, // soft_reset

{0x0D , 0x00}, // pll disable

{0x0A , 0x01}, // LVDS out clock range (25 - 30 - 47)Mhz = 001, src clock from mipi dphy = 1

{0x0B , 0x10}, // DSI clock(pixel clk = 30Mhz -> 30/30 -> dsi divider is 3 -> lvds out clk = 30

{0x10 , 0x10}, // 800*480 needs 2 lanes 0x10

{0x11 , 0x00},

{0x12 , 0x24}, // cha dsi pixel_clock * bpp / 5000 = 30000 * 6 / 5000 = 36 => 30Mhz

{0x18 , 0x6A}, // 0x79 -> single channel, 24bit mode, hs/vs low, de high : 0x7F

{0x19 , 0x00},

{0x1A , 0x02}, // default (0x03 -> 0x02)

{0x1B , 0x00},

{0x20 , 0x20}, // width = 800 -> lower part (0x20) 0x0320

{0x21 , 0x03}, // width = 800 -> upper part (0x03) 0x0320

{0x22 , 0x20}, // width = 800 -> upper part (0x03) 0x0320

{0x23 , 0x03}, // width = 800 -> upper part (0x03) 0x0320

{0x24, 0xe0}, // height = 480 -> lower part (0xe0) 0x01e0

{0x25, 0x01}, // height = 480 -> lower part (0x01) 0x01e0

{0x26 , 0xe0}, // height = 480 -> lower part (0x01) 0x01e0

{0x27 , 0x01}, // height = 480 -> lower part (0x01) 0x01e0

{0x28, 0x30}, // channel a : sync delay low, hblank = 160, vblank = 48, 48(0x30) 0x21 -> 0x30

{0x29, 0x00}, // sync delay high

{0x2A , 0x30}, // channel b

{0x2B, 0x00},

{0x2C , 0x10}, // channel a : hsync pulse width low (0x10 = 16)

{0x2D , 0x00}, // hsync pulse width high (0x10 = 16)

{0x2E , 0x10}, // channel b :

{0x2F , 0x00},

{0x30 , 0x04}, // channel a : vsync pulse width low (0x04)

{0x31 , 0x00}, // vsync pulse width high (0x04)

{0x32 , 0x04}, // channel b :

{0x33 , 0x00},

{0x34 , 0x48}, // channel a : horizontal back porch = 72(0x48)

{0x35 , 0x48}, // channel b : horizontal back porch = 72(0x48)

{0x36 , 0x16}, // channel a : vertical back porch = 22(0x16)

{0x37 , 0x16}, // channel b :

{0x38 , 0x48}, // channel a : horizontal front porch = 72(0x48)

{0x39 , 0x48}, // channel b :

{0x3A , 0x16}, // channel a : vertical front porch = 22(0x16)

{0x3B , 0x16}, // channel b :

{0x3C , 0x00}, // test pattern

{0x3D , 0x00},

{0x3E , 0x00},

{REG_ENDFLAG, 0x00},//ended flag

{0x09 , 0x01}, // soft reset

{REGFLAG_DELAY, 10}, // PLL stable delay

{0x0D , 0x01}, // PLL_EN

{REG_ENDFLAG, 0x00}, // ended flag

thanks and regards

downey kim.

  • Hello downey,
    Please use DSI Tuner to generate a .dsi file based on your configuration.
    Have you tried enabling the internal test pattern?
    Are you folllowing the power up sequence as stated in the datasheet?
    Regards
  • Hello.

    The code has been modified slightly.
    could you check the code below please.

    {0x09, 0x00}, // soft_reset
    {0x0D , 0x00}, // pll disable
    {0x0A , 0x01}, // LVDS out clock range (25 - 30 - 47)Mhz = 001, src clock from mipi dphy = 1
    //{0x0B , 0x10}, // DSI clock(pixel clk = 30Mhz -> 30/30 -> dsi divider is 3 -> lvds out clk = 30
    {0x0B , 0x28}, // DSI clock(dsi clock = half bit clock = 182Mhz -> 182/30 -> dsi divider is 6 -> lvds out clk = 30
    {0x10 , 0x10}, // 800*480 needs 2 lanes 0x10
    {0x11 , 0x00},
    //{0x12 , 0x12}, // cha dsi pixel_clock * bpp / 5000 = 30000 * 3 / 5000 = 18 => 30Mhz
    {0x12 , 0x24}, // cha dsi pixel_clock * bpp / 5000 = 60000 * 3 / 5000 = 0x24 => 30Mhz
    {0x13 , 0x24}, // chb dsi pixel_clock * divider(0x0b) / 5000 = 30000 / 5000 = 06 => 30Mhz
    {0x18 , 0x6A}, // 0x79 -> single channel, 24bit mode, hs/vs low, de high : 0x7F
    //{0x18 , 0x60}, // 0x79 -> single channel, 18bit mode, hs/vs low, de high : 0x7F
    {0x19 , 0x00},
    {0x1A , 0x02}, // default (0x03 -> 0x02)
    //{0x1A , 0x22}, // default (0x03 -> 0x02) -> reverse lvds
    {0x1B , 0x00},
    {0x20 , 0x20}, // width = 800 -> lower part (0x20) 0x0320
    {0x21 , 0x03}, // width = 800 -> upper part (0x03) 0x0320
    {0x22 , 0x20}, // width = 800 -> upper part (0x03) 0x0320
    {0x23 , 0x03}, // width = 800 -> upper part (0x03) 0x0320
    {0x24, 0xe0}, // height = 480 -> lower part (0xe0) 0x01e0
    {0x25, 0x01}, // height = 480 -> lower part (0x01) 0x01e0
    {0x26 , 0xe0}, // height = 480 -> lower part (0x01) 0x01e0
    {0x27 , 0x01}, // height = 480 -> lower part (0x01) 0x01e0
    {0x28, 0x30}, // channel a : sync delay low, hblank = 160, vblank = 48, 48(0x30) 0x21 -> 0x30
    {0x29, 0x00}, // sync delay high
    {0x2A , 0x30}, // channel b
    {0x2B, 0x00},
    {0x2C , 0x10}, // channel a : hsync pulse width low (0x10 = 16)
    {0x2D , 0x00}, // hsync pulse width high (0x10 = 16)
    {0x2E , 0x10}, // channel b :
    {0x2F , 0x00},
    {0x30 , 0x04}, // channel a : vsync pulse width low (0x04)
    {0x31 , 0x00}, // vsync pulse width high (0x04)
    {0x32 , 0x04}, // channel b :
    {0x33 , 0x00},
    {0x34 , 0x48}, // channel a : horizontal back porch = 72(0x48)
    {0x35 , 0x48}, // channel b : horizontal back porch = 72(0x48)
    {0x36 , 0x16}, // channel a : vertical back porch = 22(0x16)
    {0x37 , 0x16}, // channel b :
    {0x38 , 0x48}, // channel a : horizontal front porch = 72(0x48)
    {0x39 , 0x48}, // channel b :
    {0x3A , 0x16}, // channel a : vertical front porch = 22(0x16)
    {0x3B , 0x16}, // channel b :
    {0x3C , 0x00}, // test pattern
    {0x3D , 0x00},
    {0x3E , 0x00},
    {0xE1 , 0xFF}, //error interrrupt enable
    //{REG_ENDFLAG, 0x00},//ended flag
    {0x09 , 0x01}, // soft reset
    {REGFLAG_DELAY, 10}, // PLL stable delay
    {0x0D , 0x01}, // PLL_EN
    {REG_ENDFLAG, 0x00}, // ended flag
  • Hello joel.

    I have tried using DSI Tuner. but can`t use this program. GUI is cutting. i can`t set up for clk part.

    How do I see the screen normally?

    thanks.

  • Please, use this link to download a different DSI Tuner version.
    app.box.com/.../kg49qlg93bsseg9ewwjl0a1eg6u9aia1
  • let me know password of DSI tuner 2.1.zip file.

  • Hello, The password for the zipfile is "ti". Regads
  • Hello,
    Please, try the internal pattern mode. And for the normal operation, confirm you are following the power-up sequence correclty. Send captures.
    Regards,
    Joel
  • Hello Joel.

    I done try the test pattern mode. As a result, Test Mode runs normally.

    Please check the question below.

    1. could you check a attached file(dsi) to using DSI tuner.

    2. Do I have to follow the DSI LP11 in the Init Sequence?

    If so, should I keep LP11 when using DSI Clock as Source Clock?

    3. Does the LP11 state of the DSI signal need to make it after initializing the Mipi controller?

    Should the LP11 state be made HW?

    I appreciate your support.

    HUNTER_SN65DSI83-Q1.zip

  • Hello downey,
    It is required by the MIPI spec for the host to drive DSI outputs to LP11 prior to the transition to the HS mode. The initialization/transition sequence requirement is per the MIPI DPHY version 1.0.0 (Section 6.11) and DSI version 1.02.0 (Section 5.7) specification requirements.
    If DSI interface is driven to illegal states/protocol by the host, the SN65DSI8x may get into undesirable states.
    Regards,
    Joel
  • Hello Joel.

    How i get the documents(MIPI DPHY version 1.0.0 & DSI version 1.02.0)?

    I found a document (MIPI_D-PHY_Specification_v01-00-00). however SECTION 6.11 can not be found.

    could you provide it?

    Thanks.

    Downey.

  • Hello Downey,

    You will need to join as a member of the MIPI Alliance web site. I will contact you via email to share more details on this.

    Regards,
    Joel
  • Hello Joel,
    thanks to your support.
    I succeeded in DSI initialization. but 0XE5 register error occurred. returned value is 0X2D.

    Please look at the waveform below.

    1. reset

    2. LVDS clock

    3. DSI data

    4. DSI clock

    what is problem? could you check something wrong?

    thanks you.

  • Hello downey,
    When DSI Clock is used to derive the LVDS pixel clock, this input must remain in the HS mode during the entire video transition. If the REFCLK is used as the source for the LVDS Clock, it is allowed to stop the DSI Clock during the blanking period.

    Regards
  • Hello Joel,
    MIPI spec is MIPI Controller Power On Reset(Power On -> Reset). but EVM power can not be controlled and only RESET can be controlled.
    Is there any problem not keeping the spec?(Power On -> Reset)


    When DSI Clock is used to derive the LVDS pixel clock, this input must remain in the HS mode during the entire video transition.
    -> HS mode operates as differential
    LP mode operates as single ended
    1.2v is LP mode with blanking time
    200mV is in HS mode
    When DSI Clock is used to derive the LVDS pixel clock, Should there not be LP mode?
  • Hello downey, 

    Actually, there is no timing requirement between the Vcc power-up ramp and the EN (reset) de-assertion. The important requirement is only for the EN toggling and the DSI lanes.

    That is correct, the DSI clock should be HS continuous.

    Regards,

    Joel

  • HI Joel.

    we are made a PCB for our project. but SN65DSI83 is not operating LVDS data & Clock.

    there are some questions.

    1. Should Ten be less than 1ms?

    2. What do Init seq3 mean below table at time domain?

    3. The figure below shows the sequence measured on our board. Are there any elements of the problem?
    CH1 : Mipi_lane0_P

    CH2 : Mipi_lane0_M

    CH3 : Mipi_CLK_P

    CH4 : Mipi_CLK_M

    please check my questions.