Other Parts Discussed in Thread: SN65DSI83
Hello.
Test condition.
LCD : 800*480
using mipi 2lane, 24BPP
LVDS clock is defined by panel as 30MHz.
DSI clock is 180MHz.
CPU : MSM8974
MSM8974 MIPI <-> SN65DSI83Q1-EVM
DSI Channel A <-> LVDS Channel B <-> LCD Panel
SN65DSI83 register control does not change the screen. and LVDS data & clock is not output.
Could you check a code please. what is wrong?
{0x09, 0x00}, // soft_reset
{0x0D , 0x00}, // pll disable
{0x0A , 0x01}, // LVDS out clock range (25 - 30 - 47)Mhz = 001, src clock from mipi dphy = 1
{0x0B , 0x10}, // DSI clock(pixel clk = 30Mhz -> 30/30 -> dsi divider is 3 -> lvds out clk = 30
{0x10 , 0x10}, // 800*480 needs 2 lanes 0x10
{0x11 , 0x00},
{0x12 , 0x24}, // cha dsi pixel_clock * bpp / 5000 = 30000 * 6 / 5000 = 36 => 30Mhz
{0x18 , 0x6A}, // 0x79 -> single channel, 24bit mode, hs/vs low, de high : 0x7F
{0x19 , 0x00},
{0x1A , 0x02}, // default (0x03 -> 0x02)
{0x1B , 0x00},
{0x20 , 0x20}, // width = 800 -> lower part (0x20) 0x0320
{0x21 , 0x03}, // width = 800 -> upper part (0x03) 0x0320
{0x22 , 0x20}, // width = 800 -> upper part (0x03) 0x0320
{0x23 , 0x03}, // width = 800 -> upper part (0x03) 0x0320
{0x24, 0xe0}, // height = 480 -> lower part (0xe0) 0x01e0
{0x25, 0x01}, // height = 480 -> lower part (0x01) 0x01e0
{0x26 , 0xe0}, // height = 480 -> lower part (0x01) 0x01e0
{0x27 , 0x01}, // height = 480 -> lower part (0x01) 0x01e0
{0x28, 0x30}, // channel a : sync delay low, hblank = 160, vblank = 48, 48(0x30) 0x21 -> 0x30
{0x29, 0x00}, // sync delay high
{0x2A , 0x30}, // channel b
{0x2B, 0x00},
{0x2C , 0x10}, // channel a : hsync pulse width low (0x10 = 16)
{0x2D , 0x00}, // hsync pulse width high (0x10 = 16)
{0x2E , 0x10}, // channel b :
{0x2F , 0x00},
{0x30 , 0x04}, // channel a : vsync pulse width low (0x04)
{0x31 , 0x00}, // vsync pulse width high (0x04)
{0x32 , 0x04}, // channel b :
{0x33 , 0x00},
{0x34 , 0x48}, // channel a : horizontal back porch = 72(0x48)
{0x35 , 0x48}, // channel b : horizontal back porch = 72(0x48)
{0x36 , 0x16}, // channel a : vertical back porch = 22(0x16)
{0x37 , 0x16}, // channel b :
{0x38 , 0x48}, // channel a : horizontal front porch = 72(0x48)
{0x39 , 0x48}, // channel b :
{0x3A , 0x16}, // channel a : vertical front porch = 22(0x16)
{0x3B , 0x16}, // channel b :
{0x3C , 0x00}, // test pattern
{0x3D , 0x00},
{0x3E , 0x00},
{REG_ENDFLAG, 0x00},//ended flag
{0x09 , 0x01}, // soft reset
{REGFLAG_DELAY, 10}, // PLL stable delay
{0x0D , 0x01}, // PLL_EN
{REG_ENDFLAG, 0x00}, // ended flag
thanks and regards
downey kim.