Other Parts Discussed in Thread: TFP401
We have an application that needs to drive a 480x272@60Hz color LCD panel that has a parallel TTL, aka RGB, interface. The SoC device required by the application can only provide HDMI (and LVDS when the drivers are eventually available), forcing us to use an HDMI bridge device to drive the screen.. The problem is that the screen resolution is a fraction of VGA and thus the HDMI timing is similarly scaled, ending up at a pixel rate of 9MHz. This is far below the TFP401A 25MHz minimum RxC for 1pix/clk mode, but only around 25% below the 2pix/clk specification of 12.5MHz. We observe that the device can in fact operate at 9MHz in 1pix/clk mode, at least with the sample unit we have. Is there anything we can do externally around the device to guarantee operation at that clock frequency? We don't have a lot of alternative options for the screen as this size node almost exclusively uses the TTL/RGB interface.