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TFP401A: What are the options for running below the specified pixel clock rate?

Part Number: TFP401A
Other Parts Discussed in Thread: TFP401

We have an application that needs to drive a 480x272@60Hz color LCD panel that has a parallel TTL, aka RGB, interface.  The SoC device required by the application can only provide HDMI (and LVDS when the drivers are eventually available), forcing us to use an HDMI bridge device to drive the screen..  The problem is that the screen resolution is a fraction of VGA and thus the HDMI timing is similarly scaled, ending up at a pixel rate of 9MHz.  This is far below the TFP401A 25MHz minimum RxC for 1pix/clk mode, but only around 25% below the 2pix/clk specification of 12.5MHz.  We observe that the device can in fact operate at 9MHz in 1pix/clk mode, at least with the sample unit we have.  Is there anything we can do externally around the device to guarantee operation at that clock frequency?  We don't have a lot of alternative options for the screen as this size node almost exclusively uses the TTL/RGB interface.

  • Hello Rick,

    We have assigned a support engineer and you should be receiving a response soon.

    Regards,
    Jorge
  • Hello Rick,

    Your solution may work, however, we only characterized this device in the ranges stated in the device datasheet so we cannot guarantee the device operation.

    Regards
  • If we could tweek the timing to nudge the clock up to 12.5MHz, would that be acceptable in 1pix/clk mode, or is the internal PLL operating range electrically shifted by the mode setting? It seems to exhibit quite a lot of tolerance (>2X pixel period) in 1pix/clk mode.
  • Hello Rick,

    We have reconsidered your application and we think that the TFP401 may have issues getting the PLL to lock at frequencies lower than ~15MHz. The spec is 25MHz, but the design has some margin, but the low input frequency cut-off is ~15MHz, there is no mode the TFP401 to reduce this.

    Regards
  • The implication of your reply is that the PLL is "gearshifted" by the mode pin since the datasheet spec for 2pix/clk mode is 12.5MHz. Unless there's some internal maneuver with 2pix/clk mode like locking to both edges (otherwise the PD must be able to accept 12.5MHz) I see no other way to meet this mode spec if 15MHz is the low frequency cutoff. As I've mentioned, we have a sample COTS panel assembly running at 9MHz on RxC in 1pix/clk mode without difficulty. if 15MHz represents the design margin limit below 25MHz, our sample must come from an exceptionally good production lot.