SN75DP159: DP159 PRE_SEL , SLEW_CTL and Power on sequence

Terry Wu2

Expert 2110 points

Part Number: SN75DP159

Hello Sirs,

Need your comment and thanks in advance !

For power on sequence:

I confuse what is Vdd/Vcc and Vcc/Vdd at the same waveform timing .

Vcc is 3.3V , Vdd is 1.1V <= No power sequence for Vcc and Vdd ?

For PRE_SEL and SLEWCTL can't match in between datasheet and EVM user guide .

Which on is correct ? TKS !

This is from datasheet

This is from EVM guide

over 5 years ago

0 Malik Barton57 over 5 years ago

TI__Guru 64326 points

Terry,

When using a active reset on OE there is no specific order of Vcc or Vdd power up sequence, there is only a requirement that they come up within 200 us of each other.

Your images did not load on this side could you repost them? What does not match between datasheet and EVM user guide?

0 Terry Wu2 over 5 years ago in reply to Malik Barton57

Expert 2110 points

Hello Malik,

Thanks your reply ! Pls see below pictures.

This is from EVM .

SLEW_CTL is fatest/20ps/40ps

PRE_SEL is -5/-2.5/0 dB

This is from datasheet

SLEW_CTL is fatest/5ps/10ps

PRE_SEL is -2/0/reserve

0 Malik Barton57 over 5 years ago in reply to Terry Wu2

TI__Guru 64326 points

Terry,

Please follow the pin configurations specified in the datasheet, these settings are correct. SN75DP159 EVM Users Guides will be updated to reflect the datasheet.

Interface

Interface forum

SN75DP159: DP159 PRE_SEL , SLEW_CTL and Power on sequence