Part Number: DP83867IR
I'm working on Linux driver for DP83867 PHY IC. I'm using 4.9 vanilla kernel.
My board requires one adjustment:
- By initial bootstrap setup the "port mirroring" feature is enabled:
Reg: 0x31 (CFG4) - PORT_MIRROR_EN bit (0) is set to 1
To disable it I change this register value from 0x10b1 to 0x10b0.
Problem starts with Linux driver:
There is dp83867_phy_reset() function at ./drivers/net/phy/dp83867.c
which performs the SW_RESET (bit 15) at Control Register (CTRL - 0x001F). Such reset does full reset including registers.
And here the problem starts:
The default init code at dp83867_config_init() function leaves the PHYCR register (0x10) with value: 0x5848 (default after reset).
With such setting I see that link is up but, PHY is not working (no data transmission - checked with Wireshark).
To make it working I do write 0x4040 value to PHYCR (0x10) register.
Why do I need to do that?
What is the meaning of:
- BIT 3 - which I must clear
- BIT 11,12 - which I must clear
According to the IC datascheet (SNLS484D –FEBRUARY 2015–REVISED JULY 2016) those fields are RESERVED, RO and write to it is ignored.
DP83867 register dump:
phy_print_statusREG 0x0: 0x1140REG 0x1: 0x796dREG 0x2: 0x2000REG 0x3: 0xa231REG 0x4: 0x1e1REG 0x5: 0xc1e1REG 0x6: 0x6fREG 0x7: 0x2001REG 0x8: 0x6801REG 0x9: 0x300REG 0xa: 0x3800REG 0xb: 0x0REG 0xc: 0x0REG 0xd: 0x401fREG 0xe: 0x10b0REG 0xf: 0x3000REG 0x10: 0x4040REG 0x11: 0xbc02REG 0x12: 0x0REG 0x13: 0x1c40REG 0x14: 0x29c7REG 0x15: 0x0REG 0x16: 0x0REG 0x17: 0x40REG 0x18: 0x6150REG 0x19: 0x4040REG 0x1a: 0x2REG 0x1b: 0x0REG 0x1c: 0x0REG 0x1d: 0x0REG 0x1e: 0x2REG 0x1f: 0x0phy_regs_dump: Extended registersEXT REG 0x31: 0x10b0EXT REG 0x32: 0xd3EXT REG 0x33: 0x0EXT REG 0x6e: 0x8800EXT REG 0x6f: 0x30EXT REG 0x86: 0x37
The difference between before reset and after is only with
0x10 being 0x4040 before reset (setup from u-boot)
and 0x5848 after (when register's reset is performed)
Could somebody explain why clearing of RESERVED bits is needed?
Best regards and thanks in advance,
EFL (Ethernet & FPD Link) Applications Engineer
In reply to Rob Rodrigues:
In reply to user4759774:
Hi Łukasz, Performing a SW_RESET will reload the strap options you have selected by strap resistor. You said you have strapped Mirror Enable. Did you use a pull-up to strap to mode 4 on LED_0 pin? In the DP83867IR datasheet, mode 4 of the Mirror Enable strap is N/A meaning you should not use that mode. If you strap to mode 4, you are enabling bit in register 0x10 which is causing the error. Please verify this by reading register 0x6e. Register 0x6e maintains the options selected by strap resistor. If bit is set in register 0x6e, any time you do a reset, bit will be set in register 0x10 and you will lose your RGMII communication. Best Regards,
1. Please correct me if I'm wrong , but after SW_RESET the strap options will not be reevaluated (from HW), but values read at power up will be put to registers ?
[Rob] This is correct. During power up or RESET pulse, straps are sampled at the HW level and then stored into register 0x6e. The straps then populate the control bits they correspond to. During SW_RESET, the strap values are NOT reevaluated at the HW level, but all registers are reset and the strap values in 0x6e are used to populate the control bits again.
2. With our design we have +3V3 power supply connected to resistor. Then the resistor is connected to LED and LED connects to LED_0 pin (47). Yes, according to Figure 23 in SNLS484D we do have MODE 4..........
[Rob] By using mode 4 you are enabling Mirror mode and you are enabling a reserved function in the device.
3. And now the question - according to Table 6. - 4-level Strap Pins - the default state for Mirror Enable is 0. And we need to force Mode 3 to enable it (according to Figure 23 we can only setup Mode 1 or Mode 4) . How does it work? I do have connection for MODE 4 (N/A), which apparently causes enabling of this feature. Can you clarify ?
[Rob] The example in figure 23 shows the use of straps to set mode 1 and mode 4 on an LED. To set mode 2 or mode 3, you will need a circuit similar to the one in DP83867E customer EVM.
4. Can you reveal what is the "real" purpose of bit in register 0x10 ?
[Rob] Bit controls a hidden test mode inside of the device.
5. This behavior is as expected.
6. Could you explain why bit set at 0x0010 register (PHYCR) causes RGMII communication to be lost? Why do I have to set it back to 0 to regain RGMII connectivity? I'm asking since I will have to rationale this "quirk" patch to Linux kernel community.
[Rob] The mode 4 strap is activating the test mode which takes the interface out of RGMII. The system must clear bit to put the device back into RGMII. Because this is stated in the DS that strap mode 4 should not be used, this isn't really a "quirk".
we have connected the PHY to AM57xx.
So the RX_CTRL is connected to the CPU and the CPU has an internal PD activated while reset release. This could be also effect the AutoNeg Disable register with MODE1, which is also N/A and not allowed.
Is there also a hidden function enabled if the MODE1 is detected by the PHY?
How should this handled?
In reply to Dr. D:
Apparently the DP83867 configures itself in mode 3 without those strap pins, since the 0x006E register (STRAP_STS1) value is 0x8800.
If "autoneg" would be affected, then we would have bit 7 set in this register.
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