Hello TI team,
we have a design with a custom NXP TQMT1042 PowerPC Module located on a custom baseboard.
Both module and baseboard are new designs.
One of the TQMT1042's SGMII interfaces (1.25 Gbaud, 4 wire) is connected to a TI DP83867IS ethernet phy.
The MDI link comes up correctly as expected, autonegotiated to 1000Mbit, 100Mbit and 10Mbit against fixed speed counterparts.
However we are experiencing trouble on the SGMII interface. (All further tests have been performed with a 1000Mbit MDI link.)
Reading respective registers in the MAC and the PHY shows that the SGMII autonegotiation process has not completed. No link is established.
When disabling SGMII autonegotiation (set to fixed 1000Mbit, fdx) also no link is established.
We did a little bit of hardware inspection already:
There is a valid SGMII signal on both Tx And Rx lanes. No protocol analysing oscilloscope available at the moment unfortunately.
The MAC side PLL is locked (can be seen in the MAC's registers) and the supplying 100 MHz clock looks ok.
The PHY supplying 25 MHz clock looks also ok. MDI is also running, pointing away from PHY clock issues.
We also applied heat (hot air fan) and cooling (cooling spray) to the components to look for possible temperature dependancies, without effect.
Tx and Rx lanes each have 100nF series capacitors as demanded by the respective datasheets.
Also we looked at all relevant registers in PHY and MAC to see whether SGMII is setup correctly. This seems to be the case. For the DP83867IS you will find a register dump attached below.
We also tried setting the PHY to loopback mode and check whether the MAC now does see a link (tested with MAC SGMII ANEG active and inactive). No success.
Then we tried it the other way around (MAC loopback) to see whether the PHY does see a link (tested with PHY SGMII ANEG active and inactive). Still no success.
We would like to look a little deeper into the SGMII autonegotiation process to maybe get an idea whats going wrong here. We will try to get an oscilloscope from somewhere else in the company to examine the aneg process from the measurement side.
The only register related to the SGMII autonegotiation seems to be
SGMII Auto-Negotiation Status (SGMII_ANEG_STS), indicating
"SGMII Page Received" and "SGMII Auto-Negotiation Complete"
Are there any additional registers hidden in the PHY that refer to the SGMII autonegotiation process? This topic seems to be a bit "off-standard", we noted that PHY vendors display SGMII autonegotiation in different ways in the registers.
From past projects we also learned that other PHY vendors have "hidden" registers where SGMII/1000-Base-X electrical level and drive strengths can be altered. Does something like this exist with the DP83867IS?
Do you have any additional hints would we could try or look for?
Best regards,
Stefan Lange
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Phy register reads, loose dump
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mii write 0x03 0x0D 0x1f
mii write 0x03 0x0E 0x0037
mii write 0x03 0x0D 0x401F
mii read 0x03 0x0e
0000
0 = SGMII Auto-Negotiation process not complete.
0 = SGMII page has not been received.
mii write 0x03 0x0D 0x1f
mii write 0x03 0x0E 0x00D3
mii write 0x03 0x0D 0x401F
mii read 0x03 0x0e
0000
0 = 4-wire mode ok
mii write 0x03 0x0D 0x1f
mii write 0x03 0x0E 0x0135
mii write 0x03 0x0D 0x401F
mii read 0x03 0x0e
0000
=> mii read 0x03 0x10
5848
TX FIFO Depth 01 = 4 bytes/nibbles (1000Mbps/Other Speeds) ok
RX FIFO Depth ebenso
SGMI_EN 1 = Enable SGMII ok
FORCE_LINK_GOOD POWER_SAVE_MODE 0 = Normal operation ok
MDI_CROSSOVER 1x = Enable automatic crossover ok
=> mii read 0x03 0x11
BF02
> mii read 0x03 0x14
29C7
SGMII_AUTONEG_EN 1 ok
=> mii read 0x03 0x15
0000
receive error count
=> ping 192.168.53.100
Using FM1@DTSEC2 device
ping failed; host 192.168.53.100 is not alive
=> mii read 0x03 0x13
0000
interrupt status reg
mii write 0x03 0x0D 0x1f
mii write 0x03 0x0E 0x06e
mii write 0x03 0x0D 0x401F
mii read 0x03 0x0e
0803
1 = SGMII strapped to enable.
mii write 0x03 0x0D 0x1f
mii write 0x03 0x0E 0x0135
mii write 0x03 0x0D 0x401F
mii read 0x03 0x0e
0000
=> mii read 0x03 0x1e
0002 ok
mii write 0x03 0x0D 0x1f
mii write 0x03 0x0E 0x0031
mii write 0x03 0x0D 0x401F
mii read 0x03 0x0e
00B0
0000 0000 1001 0000
SGMII_AUTONEG_TIMER 00: 16ms maximaler Wert
