Part Number: DS90UB954-Q1
I am planning to implement functions equivalent to ALP's Margin Analysis on the SoC on my board.
So, I want to ask a few questions by looking at the ALP margin analysis script.
1. What is time_sleep (0, dwell_time) highlighted in yellow below to do?
I thought it was the waiting time from Digital reset to stabilization.
Is it correct?
2. How should I determine dwell time?
I want to know what the dwell time is 500ms.
3. A 100ms sleep is inserted everywhere as the red line is drawn.
Is this a necessary wait time?
Will shortening the time or eliminating the wait have any impact?
4. I think it is better not to delete the blue line in the 10 loops.
In other words, I think we don't need waits other than the blue line.
5. The error judgment is repeated 10 times. What is the reason for the 10th number?
Is there any difference from the case where the error is judged only once by multiplying the measurement time by 10 times?
We can help do this analysis early next week to answer your questions. Just so we make sure we are providing the right information, is the intent of this integration to allow for doing this kind of margining on startup of the system? Or would you be using it more for debugging in the prototype phase? That may determine how to best craft your solution.
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In reply to Casey McCrea:
Please also look into this app note available on Margin Analysis
FYI, Dwell time is explained in section 4 of the app note.
In reply to Vishy Viswanathan:
1, 2: Dwell time is not wait time from digital reset to stabilization. Dwell time determines how long each EQ/SP setting is monitored. When we do a manual sweep over EQ and strobe settings, after each new selection, we wait this time to see if any link error or lock failure was observed in this time.
You can see also in DS90UB954 Data Sheet section AEQ Timing (18.104.22.168.3) explanation of dwell time with respect to the builtin AEQ
3, 4: The 100ms wait time is to account for the communication delay over USB when these instructions are executed by ALP. It's better to have this delay to avoid communication errors when we do a series of device read/write accesses from PC. If you are doing margin analysis using an embedded SOC then you don't need this.
5. We test it multiple times to make sure lock is stable and there are no errors. Choosing 10 is arbitrary.
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