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XIO2001A Errata

Keith Peterson
Prodigy 60 points
Other Parts Discussed in Thread: XIO2001, XIO2000A

Is there errata available for the XIO2001A, other than the "PCIe 1.0a Device Prevent Resume from S1" app note?

We are having an issue where a 64-bit Memory Write generated on PCI is not being passed through to PCIe.  This in turn prevents subsequent completions from being passed through and causes the computer to eventually lock up.  Previous 64-bit transactions were working fine.

Thanks,

Keith Peterson

  • 0
    TI__Guru* 76130 points

    I am looking for this info and will reply soon.

    Just to confirm, there is no XIO2001A.

    Do you mean XIO2001 or XIO2000A ?

     

    Regards.

  • 0 in reply to Elias Villegas M.
    Prodigy 60 points

    Sorry. I meant XIO2000A.

    Thanks

  • 0 in reply to Keith Peterson
    TI__Guru* 76130 points

    Hello Keith,

    There is no released version of XIO2000A Errata.

    However I am attaching an image that could be useful.

    We encourage you to use the XIO2001 which is a more robust device and has fixed the erratas of the XIO2000A.

    Don't hesitate in contact us for more assistance.

    Regards.

  • 0 in reply to Elias Villegas M.
    Prodigy 60 points

    Thanks for the info.  We had already seen this errata in the XIO2000 errata.  It was supposedly fixed in the released version.  I would assume the same fix would have carried over to the XIO2000A.  Another thing is that we are not seeing a whole lot of back pressure.  The only thing happening is that there is one pending read so the PCI bus is retrying the read address over and over before the 64-bit memory write comes in and causes the hang.  There is no activity downstream that I can see.

    Unfortunately there are no plans to migrate to the XIO2001 at this time.

    We have found a temporary workaround be setting a OS registry key to disable remapping of memory over 4GB but this is not an acceptable solution.  It does, however, prove that the 64-bit write is definitely the cause of the hang.

    Thanks for your help,

    Keith Peterson

  • 0 in reply to Keith Peterson
    TI__Guru* 76130 points

    Try to disable fast back-to-back transaction enable bit 9 in the PCI Command register at offset 04h.

    Regards.

  • 0 in reply to Elias Villegas M.
    Prodigy 60 points

    Are you talking about in the XIO2000A?  If so, the bit is hardwired to 0.  Plus the transaction is being generated by a 21152 PCI-PCI bridge.

    We had already checked this.  The 21152 bridge's bit is set to 0, fast back-to-back disabled.  Analyzer traces show that fast back-to-back cycles are not occuring.

    Thanks,

    Keith Peterson